www.pudn.com > cic.rar > _primary.vhd

library verilog;
use verilog.vl_types.all;
entity dds is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        sin_out         : out    vl_logic_vector(11 downto 0);
        cos_out         : out    vl_logic_vector(11 downto 0)
    );
end dds;