www.pudn.com > cic.rar > _primary.vhd

library verilog;
use verilog.vl_types.all;
entity cic_inter is
    port(
        clk             : in     vl_logic;
        clk_inter       : in     vl_logic;
        rst             : in     vl_logic;
        nd              : in     vl_logic;
        cic_in          : in     vl_logic_vector(15 downto 0);
        cic_out         : out    vl_logic_vector(39 downto 0);
        decimator3_z    : out    vl_logic_vector(39 downto 0);
        integrator1     : out    vl_logic_vector(39 downto 0);
        integrator2     : out    vl_logic_vector(39 downto 0);
        integrator3     : out    vl_logic_vector(39 downto 0);
        integrator4     : out    vl_logic_vector(39 downto 0);
        integrator5     : out    vl_logic_vector(39 downto 0);
        decimator1      : out    vl_logic_vector(39 downto 0);
        decimator2      : out    vl_logic_vector(39 downto 0);
        decimator3      : out    vl_logic_vector(39 downto 0);
        decimator4      : out    vl_logic_vector(39 downto 0);
        decimator5      : out    vl_logic_vector(39 downto 0);
        rdy             : out    vl_logic
    );
end cic_inter;