www.pudn.com > cic.rar > _primary.vhd

library verilog;
use verilog.vl_types.all;
entity cic_4_dec is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        cic_in          : in     vl_logic_vector(15 downto 0);
        cic_out         : out    vl_logic_vector(39 downto 0);
        rdy             : out    vl_logic
    );
end cic_4_dec;