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library verilog;
use verilog.vl_types.all;
entity arrange_data is
    port(
        clk             : in     vl_logic;
        valid_in        : in     vl_logic;
        data_in         : in     vl_logic_vector(1 downto 0);
        I_data_out      : out    vl_logic_vector(14 downto 0);
        Q_data_out      : out    vl_logic_vector(14 downto 0);
        valid_out       : out    vl_logic
    );
end arrange_data;