www.pudn.com > bcm1250-src.rar > dlicpa_test.c


/*GENU#****************************************************************
* *
* ..GENERALITIES *
* *
*---------------------------------------------------------------------*
* *
* ..IDENTIFICATION: *
* ..MNAM: M.Thierauf *
* ..TITL: ldicpa.c *
* ..READ: yy/mm/dd / <author> *
* ..REVW: 13/03/02 MTh *
* *
* ..DESCRIPTION: *
* ..APPL: ethernet driver for BCM1250 internal MAC *
* ..FUNC: *
* ..TYPE: *
* *
* ..CONTENTS: *
*
*
* *
****************************************************************UNEG#*/
/*DOCR#****************************************************************
* *
* ..Documentation *
* *
*--------------------------------------------------------------------*/

/*SPEC#********************************
* ..Specification *
**************************************/
/* TLD design specification SCM HdS
3CB 05111 AAAA DDZZA*/

/* VENUS HdS API specification
3FZ 70526 AAAA DSZZA */
/*TEST#********************************
* ..testing *
**************************************/
/*****************************************************************RCOD#*/

/*DPND#****************************************************************
* *
* ..Dependancies *
* *
*--------------------------------------------------------------------*/

/*EXTD#********************************
* ..inter-swbb *
**************************************/
/*INTD#********************************
* ..intra-swbb* *
**************************************/
/*****************************************************************PNPD#*/

/*HIST#****************************************************************
* *
* ..history *
* *
*--------------------------------------------------------------------*/
/*
13/03/02: create
*/
/*CHRQ#********************************
* ..change request *
**************************************/
/*PBRP#********************************
* ..problem report *
**************************************/
/*****************************************************************TSIH#*/

/*SDEV#****************************************************************
* *
* ..DEVELOPMENT SYMBOLS *
* *
*--------------------------------------------------------------------*/

/*LIBR#********************************
* ..LIBRARIES *
**************************************/
#include "dohmDI-up.h"
#include "dlicdd_dohm.h"
#ifndef NO_VXWORKS
#include "kernelLib.h"
#endif

/*SEXT#****************************************************************
* *
* ..EXTERNAL SYMBOLS *
* *
*--------------------------------------------------------------------*/
/*LIBR#********************************
* ..LIBRARIES *
**************************************/
/*CSLT#********************************
* ..CONSTANTS *
**************************************/
uint8_t frame1[] =
{
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* Dest Addr (6)*/

0x0, 0xe0, 0x7d, 0xa2, 0xb7, 0x01, /* Source Addr (12)*/

0x08, 0x0, 0x0, 0x00, /* Type (16)*/

0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55 /* (64)*/
} ;

uint8_t frame2[] =
{
0x00, 0xe0, 0x7d, 0xa2, 0x3d, 0x24, /* Dest Addr (6)*/

0x0, 0xe0, 0x7d, 0xa2, 0xb7, 0x01, /* Source Addr (12)*/

0x08, 0x0, 0x0, 0x00, /* Type (16)*/

0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55,
0xaa, 0xaa, 0x55, 0x55 /* (64)*/
} ;


/* forward declaration */
void dlicFinit(void);

/*VARS#********************************
* ..VARIABLES *
**************************************/
extern dlicMdrv_ctrl dlicDrvCtrl[dlicCmax_dev];

static dohmMpool_buf_id dohmVbuff_pool;

static uint32_t dlicVtestcount = 0;



void dlicFdata_rec(dohmMbuf buff_id,
docxMuser_parameter user_parameter,
dohmMresult result)
{
uint32_t len;
uint32_t prot;
uchar_t *data;

prot = dohmFbuf_protocol_get(buff_id);
data = dohmFbuf_data_add_get(buff_id);
len = dohmFbuf_length_get(buff_id);

dohmFbuf_release(buff_id);
dlicVtestcount++;
}

/*PINT#****************************************************************
* *
* ..FUNCTIONAL DESCRIPTION *
* *
*---------------------------------------------------------------------*
* *
* ..INAM: dlicFtest *
* ..TITL: Regressiontest for the internal ethernet driver *
* *
*---------------------------------------------------------------------*
* NOTE: writes directly to the hardware *
****************************************************************TNIP#*/
dohmMreturn dlicFaccesstest(uint32_t idx)
{
doamMid mac;
docxMid cx_id;
int32_t rc;
uint32_t mode;

printf("\n");
/* dhhmFinit(); */

if (dohmVbuff_pool == 0)
{
dohmVbuff_pool = dohmFbuf_create("dummy", 100, 100, 100);

TESTOUT("get an access id");
docxFid(0, 0, doamFid(doamCtype_icl, idx), &amt;cx_id);

/* connect a dummy receive function */
docxFattach(&amt;cx_id,
(docxMuser_fct_to_call)dlicFdata_rec,
0 , dohmCprot_mac, dohmVbuff_pool );
}

TESTVAL("Value of idx:", idx);
mac = doamFid(doamCtype_icl, idx);
TESTVAL("Value of mac:", mac);

/* ENABLE attribute
--------------*/
TESTOUT("enable the device driver");
mode = doamCatt_ed_enable; /* enable */
rc = doamFwrite(&amt;mac, doamCatt_in_service, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);

TESTOUT("disable the device driver");
mode = doamCatt_ed_disable;
rc = doamFwrite(&amt;mac, doamCatt_in_service, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);

TESTOUT("reenable the device driver again");
mode = doamCatt_ed_enable; /* enable */
rc = doamFwrite(&amt;mac, doamCatt_in_service, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);
/* ToDo: check if the interface was actually resetted */


/* MODE attribute
--------------*/
TESTOUT("read the mode");
rc = doamFread(&amt;mac, doamCatt_mode, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);
TESTCMP("check the mode", doamCatt_full_duplex, mode);

TESTOUT("try to set the mode to half duplex");
mode = 0; /* half duplex */
rc = doamFwrite(&amt;mac, doamCatt_mode, &amt;mode );
TESTCMP("check return code", dlicCerrNotImplemented, rc);

TESTOUT("set the mode to full duplex");
mode = doamCatt_full_duplex; /* full duplex */
rc = doamFwrite(&amt;mac, doamCatt_mode, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);

/* SPEED attribute
--------------*/
#if 0
TESTOUT("read the speed");
rc = doamFread(&amt;mac, doamCatt_speed, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);
TESTCMP("check the speed", doamCatt_speed_100_M, mode);

TESTOUT("try to set the speed to 10M");
mode = doamCatt_speed_10_M;
rc = doamFwrite(&amt;mac, doamCatt_speed, &amt;mode );
TESTCMP("check return code", -1, rc);

TESTOUT("set the spped to 100M");
mode = doamCatt_speed_100_M;
rc = doamFwrite(&amt;mac, doamCatt_speed, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);
#endif
/* PROMISCUOUS attribute
-------------------*/
TESTOUT("read the address filter mode");
rc = doamFread(&amt;mac, doamCatt_promiscuous, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);
TESTCMP("check the mode", doamCatt_ed_enable, mode);

TESTOUT("try to set the mode to not promiscuous");
mode = doamCatt_ed_disable;
rc = doamFwrite(&amt;mac, doamCatt_promiscuous, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);

TESTOUT("read the address filter mode");
rc = doamFread(&amt;mac, doamCatt_promiscuous, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);
TESTCMP("check the mode", doamCatt_ed_disable, mode);

TESTOUT("set the mode to promiscuous");
mode = doamCatt_ed_enable;
rc = doamFwrite(&amt;mac, doamCatt_promiscuous, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);

TESTOUT("read the address filter mode");
rc = doamFread(&amt;mac, doamCatt_promiscuous, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);
TESTCMP("check the mode", doamCatt_ed_enable, mode);

/* LOOP attribute
-------------*/
TESTOUT("set the internal loop");
mode = doamCatt_ed_enable;
rc = doamFwrite(&amt;mac, doamCatt_loop_network, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);

TESTOUT("unset the internal loop");
mode = doamCatt_ed_disable;
rc = doamFwrite(&amt;mac, doamCatt_loop_network, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);
/* ToDo: check if the attribute was actually set */

TESTOUT("try to set the external loop");
mode = doamCatt_ed_enable;
rc = doamFwrite(&amt;mac, doamCatt_loop_line, &amt;mode );
TESTCMP("check return code", dlicCerrNotImplemented, rc);

return( 0 );
}

#if 0

void dlicFpatterntest(void)
{
int32_t rc = 0;
dohmMbuf_id buff_id;
docxMid cx_id, test_cx_attach;
int length, protocol;
char *data_addr;
uint32_t idx = 2; /* index of mac */
uint32_t i;
doamMid mac;
doeaMid macev;
uint32_t mode;
uint32_t tx_good1;
uint32_t tx_good2;
uint32_t loopcnt = 10;
uint32_t loop = 0;

if (dohmVbuff_pool == 0)
{
#ifdef __VxWorks
kernelTimeSlice(10);
#endif
dohmVbuff_pool = dohmFbuf_create("dummy", 800, 2000, dohmCprot_mac);


}

docxFid(1, 2, doamFid(doamCtype_icl, idx),
&amt;test_cx_attach);

docxFattach(&amt;test_cx_attach,
(docxMuser_fct_to_call)dlicFdata_rec,
0 , dohmCprot_mac, dohmVbuff_pool );

mac = doamFid(doamCtype_icl, idx);

dlicVtestcount = 0;

doeaFid( doeaCtype_traffic_counter, 1, mac, &amt;macev);
doeaFacc_counter_read( &amt;macev, &amt;tx_good1 );

if( loop ){
TESTOUT("set the internal loop");
mode = doamCatt_ed_enable;
rc = doamFwrite(&amt;mac, doamCatt_loop_network, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);
}

TESTOUT("enable the device driver");
mode = doamCatt_ed_enable; /* enable */
rc = doamFwrite(&amt;mac, doamCatt_in_service, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);

for( i = 0; i < loopcnt; i++ )
{
buff_id = dohmFbuf_take(dohmVbuff_pool);

if( (uint32_t)buff_id == -1 ){
printf("ERROR: buffer alloc failed");
}

docxFid(1,2, doamFid(doamCtype_icl, idx), &amt;cx_id);
length = 64;
protocol = dohmCprot_mac;

dohmFbuf_length_set(buff_id, length);
dohmFbuf_protocol_set(buff_id, protocol);
dohmFbuf_cx1_set(buff_id, cx_id);

data_addr = (char *)dohmFbuf_data_add_get(buff_id);

memcpy( data_addr, frame2, length );

rc = docxFbuffer_send(buff_id);

/* taskDelay( 1 ); */

}
dohmFsleep( 5 );

doeaFid( doeaCtype_traffic_counter, 1, mac, &amt;macev);
doeaFacc_counter_read( &amt;macev, &amt;tx_good2 );
TESTCMP("check Tx counter", loopcnt, tx_good2 - tx_good1);

TESTOUT("unset the internal loop");
mode = doamCatt_ed_disable;
rc = doamFwrite(&amt;mac, doamCatt_loop_network, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);
}
#endif
/***************************************************************
# ##### ## #####
# # # # # # #
# # # # # # #
# # # ###### # #
# # # # # # #
# # # # # # #
###### ##### # # #####
***************************************************************/
void dlicFload_rec(dohmMbuf buff_id,
docxMuser_parameter user_parameter,
dohmMresult result)
{
docxMid new_cxid;
uint32_t len;
uint32_t prot;

len = dohmFbuf_length_get(buff_id);

prot = dohmFbuf_protocol_get(buff_id);

dohmFbuf_cx1_get(buff_id, new_cxid);

dlicVtestcount++;

dohmFbuf_release(buff_id);
}

int dlicFloadtest(uint32_t idx)
{
int32_t rc = 0;
dohmMbuf_id buff_id;
docxMid cx_id, test_cx_attach;
int length, protocol;
char *data_addr;
uint32_t i;
uint32_t tx_good1;
uint32_t tx_good2;
uint32_t rx_good1;
uint32_t rx_good2;
doamMid mac;
doeaMid macev;
uint32_t mode;
uint32_t loopcnt = 1000;

if (dohmVbuff_pool == 0)
{
#ifdef __VxWorks
kernelTimeSlice(10);
#endif
dohmVbuff_pool = dohmFbuf_create("dummy", 800, 2000, dohmCprot_mac);
docxFid(1, 2, doamFid(doamCtype_icl, idx), &amt;test_cx_attach);

TESTOUT("attachen device driver");
docxFattach(&amt;test_cx_attach,
(docxMuser_fct_to_call)dlicFload_rec,
0 , dohmCprot_mac, dohmVbuff_pool );
}

mac = doamFid(doamCtype_icl, idx);

doeaFid( doeaCtype_traffic_counter, 1, mac, &amt;macev);
doeaFacc_counter_read( &amt;macev, &amt;tx_good1 );

doeaFid( doeaCtype_traffic_counter, 4, mac, &amt;macev);
doeaFacc_counter_read( &amt;macev, &amt;rx_good1 );

TESTOUT("enable the device driver");
mode = doamCatt_ed_enable; /* enable */
rc = doamFwrite(&amt;mac, doamCatt_in_service, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);

#if 0
TESTOUT("set the internal loop");
mode = doamCatt_ed_enable;
rc = doamFwrite(&amt;mac, doamCatt_loop_network, &amt;mode );
TESTCMP("check return code", dohmCreturn_ok, rc);
#endif
dlicVtestcount = 0;
TESTVAL("sending following number of testframes internally", loopcnt);

for( i = 0; i < loopcnt; i++ )
{
buff_id = dohmFbuf_take(dohmVbuff_pool);
if( (uint32_t)buff_id == -1 ){
printf("ERROR: buffer alloc failed");
return( -1 );
}

docxFid(1,2, doamFid(doamCtype_icl, idx), &amt;cx_id);
length = 64;
protocol = dohmCprot_mac;

dohmFbuf_length_set(buff_id, length);
dohmFbuf_protocol_set(buff_id, protocol);
dohmFbuf_cx1_set(buff_id, cx_id);

data_addr = (char *)dohmFbuf_data_add_get(buff_id);
memcpy( data_addr, frame1, length );

rc = docxFbuffer_send(buff_id);

dohmFsleep( 1 );

}

dohmFsleep( 1 );

doeaFid( doeaCtype_traffic_counter, 1, mac, &amt;macev);
doeaFacc_counter_read( &amt;macev, &amt;tx_good2 );

doeaFid( doeaCtype_traffic_counter, 4, mac, &amt;macev);
doeaFacc_counter_read( &amt;macev, &amt;rx_good2 );

TESTCMP("check Tx counter", loopcnt, tx_good2 - tx_good1);
TESTCMP("check Rx counter", loopcnt, rx_good2 - rx_good1);

TESTCMP("check Rx frames", loopcnt, dlicVtestcount );


return( 0 );
}


/*PINT#****************************************************************
* *
* ..FUNCTIONAL DESCRIPTION *
* *
*---------------------------------------------------------------------*
* *
* ..INAM: showTxAll *
* ..TITL: prints information about the Tx Ring *
* *
*---------------------------------------------------------------------*
* *
****************************************************************TNIP#*/
void showTxAll( uint32_t num )
{
dlicMdma_descr *pDscr;
dlicMdma_ctrl *pDma;
uint32_t idx;
uint64_t reg;
uint32_t reg_hi;
uint32_t reg_lo;
uint32_t chan = 0;


if( !((1<<num) &amt; dlicCdev_mask) ) return;

for( idx = 0; idx < NUM_TDS_DEF; idx++ )
{
pDscr = dlicDrvCtrl[num].txDma[0].dscrTable_start + idx;
printf("IDX:>d OFFS:0x>x ADDR:0x>x SOP:>d BUF:0x>x LEN:>d",
idx,
(uint32_t)(pDscr->dscr_a &amt; M_DMA_DSCRA_OFFSET),
(uint32_t)(pDscr->dscr_a &amt; M_DMA_DSCRA_A_ADDR),
(pDscr->dscr_a &amt; M_DMA_ETHTX_SOP) ? 1 : 0,
(uint32_t)((pDscr->dscr_b >> S_DMA_DSCRB_B_ADDR) &amt; 0xffffffff),
(uint32_t)G_DMA_DSCRB_PKT_SIZE(pDscr->dscr_b));

if( pDscr == dlicDrvCtrl[num].txDma[0].dscrTable_rem){
printf(" < remove");
}
if( pDscr == dlicDrvCtrl[num].txDma[0].dscrTable_add ){
printf(" < add");
}
printf("\n");
}
printf("remove: >x\n", (uint32_t)dlicDrvCtrl[num].txDma[0].dscrTable_rem );
printf("add : >x\n", (uint32_t)dlicDrvCtrl[num].txDma[0].dscrTable_add );

pDma = &amt;(dlicDrvCtrl[num].txDma[0]);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_CONFIG0);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("tx>d config0 = 0x>08x>08x \n", chan, reg_hi, reg_lo);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_CONFIG1);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("tx>d config1 = 0x>08x>08x \n", chan, reg_hi, reg_lo);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_DSCR_CNT);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("tx>d dscrcnt = 0x>08x>08x \n", chan, reg_hi, reg_lo);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_DSCR_BASE);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("tx>d dscrbase = 0x>08x>08x \n", chan, reg_hi, reg_lo);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_CUR_DSCRA);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("tx>d curdscr = 0x>08x>08x \n", chan, reg_hi, reg_lo);

printf("tx>d maxdscr = >d \n", chan, pDma->maxCount );
printf("tx>d maxAddRem = >d \n", chan, pDma->maxRemAdd );

}


/*PINT#****************************************************************
* *
* ..FUNCTIONAL DESCRIPTION *
* *
*---------------------------------------------------------------------*
* *
* ..INAM: showRxAll *
* ..TITL: prints information about the Rx Ring *
* *
*---------------------------------------------------------------------*
* *
****************************************************************TNIP#*/
void showRxAll( uint32_t num )
{
dlicMdma_descr *pDscr;
dlicMdma_ctrl *pDma;
uint32_t idx;
uint64_t reg;
uint32_t reg_hi;
uint32_t reg_lo;
uint32_t chan = 0;


if( !((1<<num) &amt; dlicCdev_mask) ) return;

for( idx = 0; idx < NUM_RDS_DEF; idx++ )
{
pDscr = dlicDrvCtrl[num].rxDma[0].dscrTable_start + idx;
printf("IDX:>i OFFS:0x>x ADDR:0x>x SOP:>i STAT:>x BUF:0x>x LEN:>i",
idx,
(uint32_t)(pDscr->dscr_a &amt; M_DMA_DSCRA_OFFSET),
(uint32_t)(pDscr->dscr_a &amt; M_DMA_DSCRA_A_ADDR),
(pDscr->dscr_a &amt; M_DMA_ETHTX_SOP) ? 1 : 0,
(uint32_t)((pDscr->dscr_a &amt; M_DMA_DSCRA_STATUS) >> S_DMA_DSCRA_STATUS),
(uint32_t)((pDscr->dscr_b >> S_DMA_DSCRB_B_ADDR) &amt; 0xffffffff),
(uint32_t)G_DMA_DSCRB_PKT_SIZE(pDscr->dscr_b));

if( pDscr == dlicDrvCtrl[num].rxDma[0].dscrTable_rem){
printf(" < remove");
}
if( pDscr == dlicDrvCtrl[num].rxDma[0].dscrTable_add ){
printf(" < add");
}
printf("\n");

}
printf("remove ptr: >x\n", dlicDrvCtrl[num].rxDma[0].dscrTable_rem );
printf("add ptr: >x\n", dlicDrvCtrl[num].rxDma[0].dscrTable_add );

pDma = &amt;(dlicDrvCtrl[num].rxDma[0]);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_CONFIG0);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("rx>d config0 = 0x>08x>08x \n", chan, reg_hi, reg_lo);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_CONFIG1);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("rx>d config1 = 0x>08x>08x \n", chan, reg_hi, reg_lo);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_DSCR_CNT);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("rx>d dscrcnt = 0x>08x>08x \n", chan, reg_hi, reg_lo);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_DSCR_BASE);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("rx>d dscrbase = 0x>08x>08x \n", chan, reg_hi, reg_lo);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_CUR_DSCRADDR);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("rx>d curdscr addr = 0x>08x>08x \n", chan, reg_hi, reg_lo);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_CUR_DSCRA);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("rx>d curdscr = 0x>08x>08x \n", chan, reg_hi, reg_lo);

printf("rx>d mindscr = >d \n", chan, pDma->minCount );
printf("tx>d minAddRem = >d \n", chan, pDma->minRemAdd );
}


/**********************************
show mac/dma/phy regs
**********************************/
void showbcmTx (int inst, int chan)
{
dlicMdma_ctrl *pDma;
uint64_t reg;
uint32_t reg_hi;
uint32_t reg_lo;

if( !((1<<inst) &amt; dlicCdev_mask) ) return;

if( (chan > 1) || (chan < 0) )
printf("channel number must be 0 or 1\n");

pDma = &amt;(dlicDrvCtrl[inst].rxDma[chan]);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_CONFIG0);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("rx>d config0 = 0x>08x>08x \n", chan, reg_hi, reg_lo);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_CONFIG1);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("rx>d config1 = 0x>08x>08x \n", chan, reg_hi, reg_lo);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_DSCR_CNT);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("rx>d dscrcnt = 0x>08x>08x \n", chan, reg_hi, reg_lo);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_DSCR_BASE);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("rx>d dscrbase = 0x>08x>08x \n", chan, reg_hi, reg_lo);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_CUR_DSCRA);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("rx>d curdscr = 0x>08x>08x \n", chan, reg_hi, reg_lo);

}

void showbcmRx (int inst, int chan)
{
dlicMdma_ctrl *pDma;
uint64_t reg;
uint32_t reg_hi;
uint32_t reg_lo;

if( !((1<<inst) &amt; dlicCdev_mask) ) return;

if( (chan > 1) || (chan < 0) )
printf("channel number must be 0 or 1\n");

pDma = &amt;(dlicDrvCtrl[inst].txDma[chan]);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_CONFIG0);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("rx>d config0 = 0x>08x>08x \n", chan, reg_hi, reg_lo);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_CONFIG1);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("rx>d config1 = 0x>08x>08x \n", chan, reg_hi, reg_lo);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_DSCR_CNT);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("rx>d dscrcnt = 0x>08x>08x \n", chan, reg_hi, reg_lo);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_DSCR_BASE);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("rx>d dscrbase = 0x>08x>08x \n", chan, reg_hi, reg_lo);

reg = SB_DMA_REG_READ(pDma, R_MAC_DMA_CUR_DSCRA);
reg_hi = (uint32_t)(reg >> 32); reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("rx>d curdscr = 0x>08x>08x \n", chan, reg_hi, reg_lo);

}


void showbcmMac (int inst)
{
uint64_t reg;
uint32_t reg_hi;
uint32_t reg_lo;

if( !((1<<inst) &amt; dlicCdev_mask) ) return;

reg = SB_MAC_REG_READ(&amt;dlicDrvCtrl[inst], R_MAC_ENABLE);
reg_hi = (uint32_t)(reg >> 32);
reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("mac macenable = 0x>08x>08x \n", reg_hi, reg_lo);

reg = SB_MAC_REG_READ(&amt;dlicDrvCtrl[inst], R_MAC_CFG);
reg_hi = (uint32_t)(reg >> 32);
reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("mac maccfg = 0x>08x>08x \n", reg_hi, reg_lo);

reg = SB_MAC_REG_READ(&amt;dlicDrvCtrl[inst], R_MAC_FRAMECFG);
reg_hi = (uint32_t)(reg >> 32);
reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("mac framecfg = 0x>08x>08x \n", reg_hi, reg_lo);

reg = SB_MAC_REG_READ(&amt;dlicDrvCtrl[inst], R_MAC_ADFILTER_CFG);
reg_hi = (uint32_t)(reg >> 32);
reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("mac rxfilter = 0x>08x>08x \n", reg_hi, reg_lo);

reg = SB_MAC_REG_READ(&amt;dlicDrvCtrl[inst], R_MAC_INT_MASK);
reg_hi = (uint32_t)(reg >> 32);
reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("mac imr = 0x>08x>08x \n", reg_hi, reg_lo);

reg = SB_MAC_REG_READ(&amt;dlicDrvCtrl[inst], R_MAC_STATUS);
reg_hi = (uint32_t)(reg >> 32);
reg_lo = (uint32_t)(reg &amt; 0xffffffff);
printf("mac isr = 0x>08x>08x \n", reg_hi, reg_lo);
}

void showbcmCtr( int idx )
{
int val;

if( !((1<<idx) &amt; dlicCdev_mask) ) return;

printf(" Mac>d - Macbase = 0x>08x\n", idx, dlicDrvCtrl[idx].macbase);

val = SB_MAC_REG_READ(&amt;dlicDrvCtrl[idx], R_MAC_RMON_TX_BYTES );
printf(" Tx Bytes : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_COLLISIONS);
printf(" Tx Collisions : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_LATE_COL );
printf(" Tx Late Coll. : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_EX_COL );
printf(" Tx Exc. Coll. : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_FCS_ERROR );
printf(" Tx FCS Error : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_TX_ABORT );
printf(" Tx Abort : >d\n", val );
/* Counter #6 (0x30) now reserved */
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_TX_BAD );
printf(" Tx Bad : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_TX_GOOD );
printf(" Tx Goods : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_TX_RUNT );
printf(" Tx Runts : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_TX_OVERSIZE);
printf(" Tx Oversize : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_RX_BYTES );
printf(" Rx Bytes : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_RX_MCAST );
printf(" Rx MCast : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_RX_BCAST );
printf(" Rx BCast : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_RX_BAD );
printf(" Rx Bad : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_RX_GOOD );
printf(" Rx Good : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_RX_RUNT );
printf(" Rx Runt : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_RX_OVERSIZE);
printf(" Rx Oversize : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_RX_FCS_ERROR);
printf(" Rx FCS Error : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_RX_LENGTH_ERROR);
printf(" Rx Length Err : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_RX_CODE_ERROR );
printf(" Rx Code Err : >d\n", val );
val = SB_MAC_REG_READ (&amt;dlicDrvCtrl[idx], R_MAC_RMON_RX_ALIGN_ERROR );
printf(" Rx Align Err : >d\n", val );
}

#if 0
int resetbcmCtr( int idx )
{
int32_t rc;

rc = dlicFinit_counter( &amt;dlicDrvCtrl[idx] );

return(rc);
}

void showPhy(int inst)
{
/* if( !((1<<inst) &amt; dlicCdev_mask) ) return; */

printf("PhyReg >02x val >04x\n",
0,
sbeth_mii_read(&amt;dlicDrvCtrl[inst], 1, 0));
printf("PhyReg >02x val >04x\n",
1,
sbeth_mii_read(&amt;dlicDrvCtrl[inst], 1, 1));

}

void phywr (int inst, int reg, int val)
{
/* if( !((1<<inst) &amt; dlicCdev_mask) ) return; */

sbeth_mii_write( &amt;dlicDrvCtrl[inst], 1, reg, val);

printf("PhyReg >02x val >04x\n",
0,
sbeth_mii_read(&amt;dlicDrvCtrl[inst], 1, reg));

}
#endif

/*FIUT#****************************************************************
* *
* ..UTS END *
* *
****************************************************************TUIF#*/