www.pudn.com > bcm1250-src.rar > dlicdd_dohm.h
#ifndef dlicdd_H
#define dlicdd_H
/*GENU#****************************************************************
* *
* ..GENERALITIES *
* *
*---------------------------------------------------------------------*
* *
* ..IDENTIFICATION: *
* ..MNAM: M.Thierauf *
* ..TITL: dlicdd.h *
* ..READ: 27/03/02 / MTh *
* ..REVW: / / / *
* *
* ..DESCRIPTION: *
* ..APPL: *
* Object handler level *
* ..FUNC: *
* ..TYPE: include *
* *
* ..CONTENTS: definitions for the internal ethernet driver *
* *
****************************************************************UNEG#*/
/*DOCR#****************************************************************
* *
* ..Documentation *
* *
*--------------------------------------------------------------------*/
/*SPEC#********************************
* ..Specification *
**************************************/
/*TEST#********************************
* ..testing *
**************************************/
/****************************************************************RCOD#*/
/*DPND#****************************************************************
* *
* ..Dependancies *
* *
*--------------------------------------------------------------------*/
/*EXTD#********************************
* ..inter-swbb *
**************************************/
/*INTD#********************************
* ..intra-swbb* *
**************************************/
/****************************************************************PNPD#*/
/*HIST#****************************************************************
* *
* ..history *
* *
*--------------------------------------------------------------------*/
/*
creation on 27/03/02
*/
/*CHRQ#********************************
* ..change request *
**************************************/
/*PBRP#********************************
* ..problem report *
**************************************/
/****************************************************************TSIH#*/
/*SDEV#****************************************************************
* *
* ..DEVELOPMENT SYMBOLS *
* *
*--------------------------------------------------------------------*/
/*LIBR#********************************
* ..LIBRARIES *
**************************************/
#ifdef NO_VXWORKS
#include "dohm-gfi-al.h"
#include "dohm-gfi-types.h"
#endif
#include "dohmDI-up.h"
#include "bcm1250.h" /* BCM1250 register definitions */
#include "bcm1250Lib.h" /* BCM1250 register definitions */
#include "A7510_scm.h" /* common project specifics */
#include "dohmDD-up.h" /* Waterj added on 030221 */
/*CSLT#********************************
* ..CONSTANTS *
**************************************/
/****************************************************************VEDS#*/
/*SPRO#****************************************************************
* *
* ..PRODUCT SYMBOLS *
* *
*--------------------------------------------------------------------*/
/*LIBR#********************************
* ..LIBRARIES *
**************************************/
/*CSLT#********************************
* ..CONSTANTS *
**************************************/
#define MII_COMMAND_START 0x01
#define MII_COMMAND_READ 0x02
#define MII_COMMAND_WRITE 0x01
#define MII_COMMAND_ACK 0x02
#define BMCR_RESET 0x8000
#define BMCR_LOOPBACK 0x4000
#define BMCR_SPEED0 0x2000
#define BMCR_ANENABLE 0x1000
#define BMCR_POWERDOWN 0x0800
#define BMCR_ISOLATE 0x0400
#define BMCR_RESTARTAN 0x0200
#define BMCR_DUPLEX 0x0100
#define BMCR_COLTEST 0x0080
#define BMCR_SPEED1 0x0040
#define BMCR_SPEED1000 (BMCR_SPEED1|BMCR_SPEED0)
#define BMCR_SPEED100 (BMCR_SPEED0)
#define BMCR_SPEED10 0
#define BMSR_100BT4 0x8000
#define BMSR_100BT_FDX 0x4000
#define BMSR_100BT_HDX 0x2000
#define BMSR_10BT_FDX 0x1000
#define BMSR_10BT_HDX 0x0800
#define BMSR_100BT2_FDX 0x0400
#define BMSR_100BT2_HDX 0x0200
#define BMSR_1000BT_XSR 0x0100
#define BMSR_PRESUP 0x0040
#define BMSR_ANCOMPLT 0x0020
#define BMSR_REMFAULT 0x0010
#define BMSR_AUTONEG 0x0008
#define BMSR_LINKSTAT 0x0004
#define BMSR_JABDETECT 0x0002
#define BMSR_EXTCAPAB 0x0001
#define K1STSR_MSMCFLT 0x8000
#define K1STSR_MSCFGRES 0x4000
#define K1STSR_LRSTAT 0x2000
#define K1STSR_RRSTAT 0x1000
#define K1STSR_LP1KFD 0x0800
#define K1STSR_LP1KHD 0x0400
#define K1STSR_LPASMDIR 0x0200
#define ANLPAR_NP 0x8000
#define ANLPAR_ACK 0x4000
#define ANLPAR_RF 0x2000
#define ANLPAR_ASYPAUSE 0x0800
#define ANLPAR_PAUSE 0x0400
#define ANLPAR_T4 0x0200
#define ANLPAR_TXFD 0x0100
#define ANLPAR_TXHD 0x0080
#define ANLPAR_10FD 0x0040
#define ANLPAR_10HD 0x0020
#define ANLPAR_PSB 0x0001 /* 802.3 */
#define PHYIDR1 0x2000
#define PHYIDR2 0x5C60
#define MII_BMCR 0x00 /* Basic mode control register (rw) */
#define MII_BMSR 0x01 /* Basic mode status register (ro) */
#define MII_K1STSR 0x0A /* 1K Status Register (ro) */
#define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */
#define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */
/*DATS#********************************
* ..DATA STRUCTURES *
**************************************/
/*VARS#********************************
* ..VARIABLES *
**************************************/
/****************************************************************ORPS#*/
/*SEXT#****************************************************************
* *
* ..EXTERNAL SYMBOLS *
* *
*--------------------------------------------------------------------*/
/*LIBR#********************************
* ..LIBRARIES *
**************************************/
#ifdef VXWORKS_AL
#define dlicCmax_dev 2 /* max available devices */
#else
#define dlicCmax_dev 3 /* max available devices */
#endif /*VXWORKS_AL*/
#ifdef __VxWorks
#define dlicCdev_mask 3 /* selects available devices */
#else
#define dlicCdev_mask 7 /* selects available devices */
#endif
#define dlicCpollRate 5 /* only for vxWorks (unit ticks) */
#define SB_DEV_NAME "icl "
#define SB_DEV_NAME_LEN 4
#define VXW_RCV_BUF_OFFSET 2
#define ETH_CRC_LEN 4
#define EADDR_LEN 6 /* ethernet address length */
#define NUM_RDS_DEF 128 /* default number of rx dscrs */
#define NUM_TDS_DEF 64 /* default number of tx dscrs */
#define MAC0_REG_OFFSET 0x4000
#define MAC1_REG_OFFSET 0x5000
#define MAC2_REG_OFFSET 0x6000
#define MAC_BUFFER_SIZE 1600 /* NOTE: The real value should be taken from SW */
typedef uint32_t sbmac_port_t;
typedef uint64_t sbmac_physaddr_t;
typedef uint64_t sbmac_enetaddr_t;
typedef enum {
sbmac_speed_10,
sbmac_speed_100,
sbmac_speed_1000
} sbmac_speed_t;
typedef enum {
sbmac_duplex_half,
sbmac_duplex_full
} sbmac_duplex_t;
typedef enum {
sbmac_fc_disabled,
sbmac_fc_frame,
sbmac_fc_collision,
sbmac_fc_carrier
} sbmac_fc_t;
typedef enum {
dlicCstate_fault = 0,
dlicCstate_init = 1,
dlicCstate_ready = 2,
dlicCstate_enabled = 3
} dlicMstate;
typedef enum {
dlicCok = 0,
dlicCerrNotImplemented = -1,
dlicCerrWrongType = -2,
dlicCerrWrongAttr = -3,
dlicCerrWrongNum = -4,
dlicCerrOutOfRange = -5,
dlicCerrInternal = -6,
dlicCerrState = -7,
dlicCerrAlignement = -8,
dlicCerrInit = -9,
dlicCerrRxDMA = -10,
dlicCerrRxOverflow = -11,
dlicCerrTxDMA = -12,
dlicCerrTxOverflow = -13,
dlicCerrAlloc = -14,
dlicCerrBadFrame = -15,
dlicCerrNoBuffers = -16
} dlicMerror;
#define CACHELINESIZE 32
#define NUMCACHEBLKS(x) (((x)+CACHELINESIZE-1)/CACHELINESIZE)
#define SB1250_MAC_SPEED_10 10000000 /* 10 Mbps */
#define SB1250_MAC_SPEED_100 100000000 /* 100 Mbps */
#define SB1250_MAC_SPEED_1000 1000000000 /* 1000 Mbps - 1Gbps */
#define SB1250_MAC_SPEED_DEF SB1250_MAC_SPEED_10
#define BUF_TYPE_CL 0x1 /* this's a cluster pointer */
#define BUF_TYPE_MBLK 0x2 /* this's a mblk pointer */
#define PKT_TYPE_MULTI 0x1 /* packet with a multicast address */
#define PKT_TYPE_UNI 0x2 /* packet with a unicast address */
#define PKT_TYPE_NONE 0x4 /* address type is not meaningful */
/* Register Access
---------------*/
#ifndef SB_MAC_REG_READ
#define SB_MAC_REG_READ(ctrl, reg) \
MIPS3_LD((ctrl)->macbase + (reg))
#endif /* SB1250_MAC_REG_READ */
#ifndef SB_MAC_REG_WRITE
#define SB_MAC_REG_WRITE(ctrl, reg, val) \
MIPS3_SD(((ctrl)->macbase + (reg)), (val));
#endif /* SB1_MAC_REG_WRITE */
#ifndef SB_DMA_REG_READ
#define SB_DMA_REG_READ(ctrl, reg) \
MIPS3_LD((ctrl)->dmabase + (reg))
#endif /* SB_DMA_REG_READ */
#ifndef SB_DMA_REG_WRITE
#define SB_DMA_REG_WRITE(ctrl, reg, val) \
MIPS3_SD(((ctrl)->dmabase + (reg)), (val));
#endif /* SB_DMA_REG_WRITE */
/*****************************************************************************/
/*****************************************************************************/
/* DMA Descriptor
--------------*/
typedef struct dlicMdma_descr {
uint64_t dscr_a;
uint64_t dscr_b;
} dlicMdma_descr;
/* used format:
Descriptor A: status flags size addr offset
------------------------------------------------
bit: 63:51 50:49 48:40 39:5 4:0
Descriptor B: length flags etheVbuf reserv options
----------------------------------------------------
bit: 63:49 50 48:5 5 3:0
*/
/* Data structure
============== */
typedef struct dlicMdma_ctrl {
/*
* This stuff is used to identify the channel and the registers
* associated with it.
*/
/* NOTE: DMA Descriptors MUST be aligned to cache line boundaries */
/* WARNING: GNU specific extension!!!! */
dlicMdma_descr *dscrTable;
uchar_t *dmabase;
uint32_t channel; /* channel number */
uint32_t txdir; /* direction (1=transmit) */
uint32_t maxdescr; /* total # of descriptors in ring */
uint32_t dscr_count; /* current descriptor count */
/*
* This stuff is for maintenance of the ring
*/
dlicMdma_descr *dscrTable_start; /* base of descriptor table */
dlicMdma_descr *dscrTable_end; /* end of descriptor table */
dlicMdma_descr *dscrTable_add; /* next dscr for sw to add */
dlicMdma_descr *dscrTable_rem; /* next dscr for sw to remove */
uint32_t maxRemAdd; /* max distance remove and add */
uint32_t minRemAdd; /* min distance remove and add */
uint32_t maxCount; /* max descriptor count */
uint32_t minCount; /* min descriptor count */
uint32_t tx_bc_mcFrame;
uint32_t lastStatus;
} dlicMdma_ctrl;
/* Operations on Rx Rings:
=======================*/
/* Setup Ring
----------*/
dlicMerror dlicFsetup_RxRing(dlicMdma_ctrl* pDma_ctrl, uint32_t macnum);
/* create an empty Rx Ring */
/* reset and initialize the DMA register */
/* Check Ready
----------- */
bool_t dlicFcheck_RxReady(dlicMdma_ctrl* pDma_ctrl);
/* just look for buffers that were received */
/* Get Packet
---------- */
dlicMerror dlicFget_RxFrame(dlicMdma_ctrl* pDma_ctrl,
dohmMbuf_id *buf_id);
/* read data from the Rx Ring and mark it as free */
/* Add Buffer
---------- */
dlicMerror dlicFadd_RxBuffer(dlicMdma_ctrl* pDma_ctrl,
dohmMbuf_id buf_id);
/* fill in a new buffer in the ring */
dohmMbuf_id dlicFfree_RxBuffer(dlicMdma_ctrl* pDma_ctrl,
uint32_t idx);
/* used to deallocate all buffers */
/* Operations on Tx Rings:
=======================*/
/* Setup Ring
----------*/
dlicMerror dlicFsetup_TxRing(dlicMdma_ctrl* pDma_ctrl, uint32_t macnum);
/* create an empty Rx Ring */
/* reset and initialize the DMA register */
/* Send Packet
----------- */
dlicMerror dlicFsend_TxFrame(dlicMdma_ctrl* pDma_ctrl,
dohmMbuf_id buf_id);
/* fill an descriptor with packet data and start DMA */
/* buffers that are already sent are removed? */
/* Check Ready
------------ */
bool_t dlicFcheck_TxReady(dlicMdma_ctrl* pDma_ctrl);
/* check if buffers are transmitted in the queue */
/* Check Ready
------------ */
dohmMbuf_id dlicFget_TxReady(dlicMdma_ctrl* pDma_ctrl);
/* get a transmitted buffer */
/*****************************************************************************/
/*****************************************************************************/
typedef struct dlicMdrv_ctrl {
/* higher level data */
char name[4];
uint32_t devNo; /* Mac Device Number */
char enetAddr[6]; /* ethernet address */
dlicMstate state; /* state of the driver*/
docxMuser_fct_to_call function_to_call; /* recevie callback */
docxMuser_parameter parameter;
dohmMprot protocol;
dohmMpool_buf_id pool_id; /* not really used yet */
uint32_t receivedFrame; /* counters */
uint32_t damagedFrame;
uint32_t sentFrame;
uint32_t releasedFrame;
uint32_t txOverflow;
uint32_t DmaError;
uint32_t RxInternalError;
/* hardware access data */
uchar_t *macbase;
sbmac_speed_t speed;
sbmac_duplex_t duplex;
sbmac_fc_t fc;
doamMatt_ed promiscious;
uint32_t phyAddr; /* phy address */
dlicMdma_ctrl txDma[2];
dlicMdma_ctrl rxDma[2];
} dlicMdrv_ctrl;
/* Hardware Access functions
-------------------------*/
dlicMerror dlicFinit_hw(dlicMdrv_ctrl *pDrvCtrl);
dlicMerror dlicFinit_counter(dlicMdrv_ctrl *pDrvCtrl);
dlicMerror dlicFdisable_hw(dlicMdrv_ctrl *pDrvCtrl);
dlicMerror dlicFenable_hw(dlicMdrv_ctrl *pDrvCtrl);
dlicMerror dlicFsetSpeed( dlicMdrv_ctrl *pDrvCtrl,
sbmac_speed_t speed );
dlicMerror dlicFsetDuplex(dlicMdrv_ctrl *pDrvCtrl,
sbmac_duplex_t duplex,
sbmac_fc_t fc);
unsigned int sbeth_mii_read(dlicMdrv_ctrl * drvctrl,
int phyaddr,
int regidx);
void sbeth_mii_write(dlicMdrv_ctrl * drvctrl,
int phyaddr,
int regidx,
unsigned int regval);
#endif