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LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY TESTCTL IS 
    PORT (CLK : IN STD_LOGIC;                 -- 1Hz 
        TSTEN : OUT STD_LOGIC;                -- 计数器时钟使能 
      CLR_CNT : OUT STD_LOGIC;                 -- 计数器清零 
         Load : OUT STD_LOGIC    );           -- 输出锁存信号 
 END TESTCTL; 
ARCHITECTURE behav OF TESTCTL IS 
    SIGNAL Div2CLK : STD_LOGIC; 
BEGIN 
    PROCESS( CLK ) 
    BEGIN 
        IF CLK'EVENT AND CLK = '1' THEN      -- 1Hz时钟2分频 
            Div2CLK <= NOT Div2CLK; 
        END IF; 
    END PROCESS; 
    PROCESS (CLK, Div2CLK) 
    BEGIN 
        IF CLK = '0' AND Div2CLK = '0' THEN  -- 产生计数器清零信号 
            CLR_CNT <= '1'; 
        ELSE 
            CLR_CNT <= '0'; 
        END IF; 
    END PROCESS; 
    Load  <= NOT Div2CLK;    TSTEN <= Div2CLK; 
END behav;