www.pudn.com > ep1c6_12_1_2_moto.rar > STEP_A.QSF
# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any other # associated documentation or information provided by Altera or a partner # under Altera's Megafunction Partnership Program may be used only # to program PLD devices (but not masked PLD devices) from Altera. Any # other use of such megafunction design, netlist, support information, # device programming or simulation file, or any other related documentation # or information is prohibited for any other purpose, including, but not # limited to modification, reverse engineering, de-compiling, or use with # any other silicon devices, unless such use is explicitly licensed under # a separate agreement with Altera or a megafunction partner. Title to the # intellectual property, including patents, copyrights, trademarks, trade # secrets, or maskworks, embodied in any such megafunction design, netlist, # support information, device programming or simulation file, or any other # related documentation or information provided by Altera or a megafunction # partner, remains with Altera, the megafunction partner, or their respective # licensors. No other licenses, including any licenses needed under any third # party's intellectual property, are provided herein. # The default values for assignments are stored in the file # step_a_assignment_defaults.qdf # If this file doesn't exist, and for assignments not listed, see file # assignment_defaults.qdf # Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # Project-Wide Assignments # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:00:20 JANUARY 28, 2005" set_global_assignment -name LAST_QUARTUS_VERSION 4.1 set_global_assignment -name VHDL_FILE decd.vhd set_global_assignment -name VHDL_FILE cnt5.vhd set_global_assignment -name GDF_FILE speed.gdf set_global_assignment -name VHDL_FILE cnt24.vhd set_global_assignment -name GDF_FILE speed_1.gdf set_global_assignment -name VHDL_FILE cnt2.vhd set_global_assignment -name GDF_FILE cmp3.gdf set_global_assignment -name VHDL_FILE cnt8.vhd set_global_assignment -name GDF_FILE cntb.gdf set_global_assignment -name VHDL_FILE cnt.vhd set_global_assignment -name VHDL_FILE reg.vhd set_global_assignment -name VHDL_FILE testctl.vhd set_global_assignment -name VHDL_FILE freqtest.vhd set_global_assignment -name VHDL_FILE lcnt8.vhd set_global_assignment -name VHDL_FILE dec1.vhd set_global_assignment -name VHDL_FILE dec2.vhd set_global_assignment -name GDF_FILE step_a.gdf set_global_assignment -name BDF_FILE step_a.bdf set_global_assignment -name SIGNALTAP_FILE stp1.stp # Pin & Location Assignments # ========================== set_location_assignment PIN_233 -to Z_F set_location_assignment PIN_239 -to S set_location_assignment PIN_234 -to D_STP set_location_assignment PIN_28 -to clk0 set_location_assignment PIN_136 -to D\[15\] set_location_assignment PIN_135 -to D\[14\] set_location_assignment PIN_134 -to D\[13\] set_location_assignment PIN_133 -to D\[12\] set_location_assignment PIN_132 -to D\[11\] set_location_assignment PIN_128 -to D\[10\] set_location_assignment PIN_41 -to D\[9\] set_location_assignment PIN_21 -to D\[8\] set_location_assignment PIN_20 -to D\[7\] set_location_assignment PIN_19 -to D\[6\] set_location_assignment PIN_18 -to D\[5\] set_location_assignment PIN_17 -to D\[4\] set_location_assignment PIN_16 -to D\[3\] set_location_assignment PIN_15 -to D\[2\] set_location_assignment PIN_14 -to D\[1\] set_location_assignment PIN_13 -to D\[0\] set_location_assignment PIN_218 -to CNTT set_location_assignment PIN_224 -to Y\[3\] set_location_assignment PIN_223 -to Y\[2\] set_location_assignment PIN_222 -to Y\[1\] set_location_assignment PIN_219 -to Y\[0\] set_location_assignment PIN_225 -to F set_location_assignment PIN_162 -to DLED\[1\] set_location_assignment PIN_161 -to DLED\[0\] set_location_assignment PIN_152 -to clk5 set_location_assignment PIN_240 -to u_d set_location_assignment PIN_226 -to Z # Timing Assignments # ================== set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS OFF # Analysis & Synthesis Assignments # ================================ set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL SYNPLIFY set_global_assignment -name FAMILY Cyclone set_global_assignment -name AUTO_LCELL_INSERTION ON set_global_assignment -name TOP_LEVEL_ENTITY step_a # Fitter Assignments # ================== set_global_assignment -name DEVICE EP1C6Q240C8 set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL" set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name MAX7000B_VCCIO_IOBANK1 3.3V set_global_assignment -name MAX7000B_VCCIO_IOBANK2 3.3V set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL # Timing Analysis Assignments # =========================== set_global_assignment -name EXCLUDE_TPD_PATHS_LESS_THAN 0.0NS # Assembler Assignments # ===================== set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS1 # Simulator Assignments # ===================== set_global_assignment -name START_TIME 0.0ns set_global_assignment -name GLITCH_INTERVAL 0.0ns set_global_assignment -name END_TIME 200.0us # SignalTap II Assignments # ======================== set_global_assignment -name ENABLE_SIGNALTAP On set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp # LogicLock Region Assignments # ============================ set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT off # --------------------------------------------- # start EDA_TOOL_SETTINGS(eda_design_synthesis) # Analysis & Synthesis Assignments # ================================ set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis # end EDA_TOOL_SETTINGS(eda_design_synthesis) # ------------------------------------------- # --------------------------------------- # start AUTO_INSERT_SLD_NODE_ENTITY(moto) # SignalTap II Assignments # ======================== set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id moto set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=M4K" -section_id moto set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id moto set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to clk5 -section_id moto set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[0\] -to F -section_id moto set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[1\] -to Y\[0\] -section_id moto set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[2\] -to Y\[1\] -section_id moto set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[3\] -to Y\[2\] -section_id moto set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[4\] -to Y\[3\] -section_id moto set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[5\] -to Z -section_id moto set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[6\] -to clk0 -section_id moto set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in\[7\] -to cntout -section_id moto set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[0\] -to F -section_id moto set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[1\] -to Y\[0\] -section_id moto set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[2\] -to Y\[1\] -section_id moto set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[3\] -to Y\[2\] -section_id moto set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[4\] -to Y\[3\] -section_id moto set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[5\] -to Z -section_id moto set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[6\] -to clk0 -section_id moto set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in\[7\] -to cntout -section_id moto set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT trigger_in -to clk0 -section_id moto set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=8" -section_id moto set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=8" -section_id moto set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=402681344" -section_id moto set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=36472" -section_id moto set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=47858" -section_id moto set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BIT_CNTR_BITS=3" -section_id moto set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id moto set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=2048" -section_id moto set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_MEM_ADDRESS_BITS=11" -section_id moto set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=1" -section_id moto set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id moto set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id moto set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id moto # end AUTO_INSERT_SLD_NODE_ENTITY(moto) # -------------------------------------