www.pudn.com > ep1c6_12_1_2_moto.rar > ROM3.VHD
-- megafunction wizard: %LPM_ROM% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: rom3.vhd -- Megafunction Name(s): -- altsyncram -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 4.1 Build 181 06/29/2004 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2004 Altera Corporation --Any megafunction design, and related netlist (encrypted or decrypted), --support information, device programming or simulation file, and any other --associated documentation or information provided by Altera or a partner --under Altera's Megafunction Partnership Program may be used only --to program PLD devices (but not masked PLD devices) from Altera. Any --other use of such megafunction design, netlist, support information, --device programming or simulation file, or any other related documentation --or information is prohibited for any other purpose, including, but not --limited to modification, reverse engineering, de-compiling, or use with --any other silicon devices, unless such use is explicitly licensed under --a separate agreement with Altera or a megafunction partner. Title to the --intellectual property, including patents, copyrights, trademarks, trade --secrets, or maskworks, embodied in any such megafunction design, netlist, --support information, device programming or simulation file, or any other --related documentation or information provided by Altera or a megafunction --partner, remains with Altera, the megafunction partner, or their respective --licensors. No other licenses, including any licenses needed under any third --party's intellectual property, are provided herein. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; ENTITY rom3 IS PORT ( address : IN STD_LOGIC_VECTOR (4 DOWNTO 0); inclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END rom3; ARCHITECTURE SYN OF rom3 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0); COMPONENT altsyncram GENERIC ( intended_device_family : STRING; width_a : NATURAL; widthad_a : NATURAL; numwords_a : NATURAL; operation_mode : STRING; outdata_reg_a : STRING; address_aclr_a : STRING; outdata_aclr_a : STRING; width_byteena_a : NATURAL; init_file : STRING; lpm_hint : STRING; lpm_type : STRING ); PORT ( clock0 : IN STD_LOGIC ; address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(15 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( intended_device_family => "Cyclone", width_a => 16, widthad_a => 5, numwords_a => 32, operation_mode => "ROM", outdata_reg_a => "UNREGISTERED", address_aclr_a => "NONE", outdata_aclr_a => "NONE", width_byteena_a => 1, init_file => "PWM_1.mif", lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=rom4", lpm_type => "altsyncram" ) PORT MAP ( clock0 => inclock, address_a => address, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: WidthData NUMERIC "16" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "5" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -- Retrieval info: PRIVATE: SingleClock NUMERIC "0" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "PWM_1.MIF" -- Retrieval info: PRIVATE: UseLCs NUMERIC "0" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" -- Retrieval info: PRIVATE: JTAG_ID STRING "rom4" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" -- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: CONSTANT: INIT_FILE STRING "PWM_1.MIF" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=rom4" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL address[4..0] -- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] -- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT NODEFVAL inclock -- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0 -- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 inclock 0 0 0 0 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL rom3.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL rom3.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL rom3.cmp FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL rom3.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL rom3_inst.vhd FALSE