www.pudn.com > ep1c6_12_1_2_moto.rar > REG.VHD

-- megafunction wizard: %LPM_FF% 
-- GENERATION: STANDARD 
-- VERSION: WM1.0 
-- MODULE: lpm_ff  
 
-- ============================================================ 
-- File Name: REG.vhd 
-- Megafunction Name(s): 
-- 			lpm_ff 
-- ============================================================ 
-- ************************************************************ 
-- THIS IS A WIZARD GENERATED FILE. DO NOT EDIT THIS FILE! 
-- ************************************************************ 
 
 
--	Copyright (C) 1988-2000 Altera Corporation 
 
--	Any megafunction design, and related net list (encrypted or decrypted), 
--	support information, device programming or simulation file, and any other 
--	associated documentation or information provided by Altera or a partner 
--	under Altera's Megafunction Partnership Program may be used only to 
--	program PLD devices (but not masked PLD devices) from Altera.  Any other 
--	use of such megafunction design, net list, support information, device 
--	programming or simulation file, or any other related documentation or 
--	information is prohibited for any other purpose, including, but not 
--	limited to modification, reverse engineering, de-compiling, or use with 
--	any other silicon devices, unless such use is explicitly licensed under 
--	a separate agreement with Altera or a megafunction partner.  Title to 
--	the intellectual property, including patents, copyrights, trademarks, 
--	trade secrets, or maskworks, embodied in any such megafunction design, 
--	net list, support information, device programming or simulation file, or 
--	any other related documentation or information provided by Altera or a 
--	megafunction partner, remains with Altera, the megafunction partner, or 
--	their respective licensors.  No other licenses, including any licenses 
--	needed under any third party's intellectual property, are provided herein. 
 
LIBRARY ieee; 
USE ieee.std_logic_1164.all; 
 
ENTITY REG IS 
	PORT 
	( 
		clock		: IN STD_LOGIC ; 
		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0); 
		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0) 
	); 
END REG; 
 
 
ARCHITECTURE SYN OF REG IS 
 
	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (15 DOWNTO 0); 
 
 
 
	COMPONENT lpm_ff 
	GENERIC ( 
		lpm_width		: NATURAL; 
		lpm_fftype		: STRING 
	); 
	PORT ( 
			clock	: IN STD_LOGIC ; 
			q	: OUT STD_LOGIC_VECTOR (15 DOWNTO 0); 
			data	: IN STD_LOGIC_VECTOR (15 DOWNTO 0) 
	); 
	END COMPONENT; 
 
BEGIN 
	q    <= sub_wire0(15 DOWNTO 0); 
 
	lpm_ff_component : lpm_ff 
	GENERIC MAP ( 
		LPM_WIDTH => 16, 
		LPM_FFTYPE => "DFF" 
	) 
	PORT MAP ( 
		clock => clock, 
		data => data, 
		q => sub_wire0 
	); 
 
 
 
END SYN; 
 
-- ============================================================ 
-- CNX file retrieval info 
-- ============================================================ 
-- Retrieval info: PRIVATE: nBit NUMERIC "32" 
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" 
-- Retrieval info: PRIVATE: DFF NUMERIC "1" 
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0" 
-- Retrieval info: PRIVATE: SCLR NUMERIC "0" 
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" 
-- Retrieval info: PRIVATE: SSET NUMERIC "0" 
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" 
-- Retrieval info: PRIVATE: SSETV NUMERIC "0" 
-- Retrieval info: PRIVATE: ACLR NUMERIC "0" 
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" 
-- Retrieval info: PRIVATE: ASET NUMERIC "0" 
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" 
-- Retrieval info: PRIVATE: ASETV NUMERIC "0" 
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" 
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF" 
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock 
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0] 
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] 
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 
-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 
-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0