www.pudn.com > ep1c6_12_1_2_moto.rar > FREQTEST.VHD

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
ENTITY FREQTEST IS 
    PORT ( CLK : IN STD_LOGIC;   
          FSIN : IN STD_LOGIC; 
          CCOUT: OUT STD_LOGIC; 
          DOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); 
END FREQTEST; 
ARCHITECTURE struc OF FREQTEST IS 
COMPONENT TESTCTL 
    PORT ( CLK : IN STD_LOGIC;     TSTEN : OUT STD_LOGIC;  
       CLR_CNT : OUT STD_LOGIC;     Load : OUT STD_LOGIC   ); 
END COMPONENT; 
COMPONENT CNT 
    PORT (    CLOCK : IN STD_LOGIC;   
               ACLR : IN STD_LOGIC;  
             CLK_EN : IN STD_LOGIC; 
                  Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); 
               COUT : OUT STD_LOGIC ); 
END COMPONENT; 
COMPONENT REG 
    PORT (   CLOCK : IN STD_LOGIC; 
              DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); 
                 Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); 
END COMPONENT; 
    SIGNAL TSTEN1 : STD_LOGIC; 
    SIGNAL CLR_CNT1 : STD_LOGIC; 
    SIGNAL Load1 : STD_LOGIC; 
    SIGNAL DTO1 : STD_LOGIC_VECTOR(15 DOWNTO 0); 
BEGIN 
  U1 : TESTCTL  PORT MAP( CLK =>CLK,    TSTEN => TSTEN1, CLR_CNT => CLR_CNT1, Load => Load1 ); 
  U2 :      REG PORT MAP( CLOCK => Load1, DATA => DTO1,Q => DOUT); 
  U3 :   CNT  PORT MAP(CLOCK => FSIN,ACLR => CLR_CNT1,CLK_EN => TSTEN1, Q => DTO1,COUT => CCOUT ); 
END struc;