www.pudn.com > ep1c6_12_1_2_moto.rar > CNT24.VHD

LIBRARY IEEE;                                            -- 24½øÖƼÆÊýÆ÷ 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY CNT24 IS 
    PORT ( CLK,EN, U_D : IN STD_LOGIC;  
             CQ : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); 
END CNT24; 
ARCHITECTURE behav OF CNT24 IS 
    SIGNAL CQI : STD_LOGIC_VECTOR(4 DOWNTO 0); 
BEGIN 
    PROCESS(CLK, EN, U_D) 
    BEGIN 
        IF EN = '1' THEN   CQI <= CQI; 
        ELSIF CLK'EVENT AND CLK = '1' THEN 
            IF U_D = '1' THEN  CQI <= CQI + 1; 
				ELSE CQI<= CQI-1;  END IF; 
        END IF; 
    END PROCESS; 
  CQ(4 DOWNTO 0) <= CQI; 
END behav;