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LIBRARY IEEE;                                            -- 4½øÖƼÆÊýÆ÷ 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY CNT2 IS 
    PORT ( CLK : IN STD_LOGIC; 
             CQ : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)); 
END CNT2; 
ARCHITECTURE behav OF CNT2 IS 
    SIGNAL CQI : STD_LOGIC_VECTOR(1 DOWNTO 0); 
BEGIN 
    PROCESS(CLK) 
    BEGIN 
       IF CLK'EVENT AND CLK = '1'  then  
                    CQI <= CQI + 1; 
         END IF; 
    END PROCESS; 
  CQ <= CQI; 
END behav;