www.pudn.com > remotepro.rar > s0l.map
78K/0 Series Linker V3.80 Date:26 Oct 2007 Page: 1
Command: -fmain.plk
Para-file: -yC:\NECTools32\DEV\
-omain.lmf
C:\NECTools32\LIB78K0\s0l.rel
-go256
-bcl0x.lib
-bcl0.lib
-bcl0f.lib
-s
main.rel
option.rel
time0.rel
interrput.rel
SPILCD.rel
systeminit.rel
Remote.rel
Out-file: main.lmf
Map-file: s0l.map
Direc-file:
Directive:
*** Link information ***
19 output segment(s)
138AH byte(s) real data
569 symbol(s) defined
*** Memory map ***
SPACE=REGULAR
MEMORY=ROM
BASE ADDRESS=00000H SIZE=08000H
OUTPUT INPUT INPUT BASE SIZE
SEGMENT SEGMENT MODULE ADDRESS
@@VECT00 00000H 00002H CSEG AT
@@VECT00 @cstart 00000H 00002H
* gap (Not Free Area) * 00002H 00002H
* gap * 00004H 0001CH
@@VECT20 00020H 00002H CSEG AT
@@VECT20 time0 00020H 00002H
* gap * 00022H 0000EH
@@VECT30 00030H 00002H CSEG AT
@@VECT30 interrpu 00030H 00002H
* gap * 00032H 0000EH
@@CALT 00040H 00000H CSEG CALLT0
@@CALT @cstart 00040H 00000H
@@CALT main 00040H 00000H
@@CALT time0 00040H 00000H
@@CALT interrpu 00040H 00000H
@@CALT SPILCD 00040H 00000H
@@CALT systemin 00040H 00000H
@@CALT Remote 00040H 00000H
* gap * 00040H 00040H
OPT_SET 00080H 00004H CSEG AT
78K/0 Series Linker V3.80 Date:26 Oct 2007 Page: 2
OPT_SET option 00080H 00004H
ONC_SET 00084H 00001H CSEG AT
ONC_SET option 00084H 00001H
@@R_INIS 00085H 00000H CSEG UNITP
@@R_INIS @cstart 00085H 00000H
@@R_INIS main 00085H 00000H
@@R_INIS time0 00085H 00000H
@@R_INIS interrpu 00085H 00000H
@@R_INIS SPILCD 00085H 00000H
@@R_INIS systemin 00085H 00000H
@@R_INIS Remote 00085H 00000H
@@R_INIS @rom 00085H 00000H
?CSEGSI 00085H 0000AH CSEG SECUR_ID
?CSEGSI option 00085H 0000AH
* gap (Not Free Area) * 0008FH 00101H
@@R_INIT 00190H 0000CH CSEG UNITP
@@R_INIT @cstart 00190H 00000H
@@R_INIT main 00190H 00000H
@@R_INIT time0 00190H 00000H
@@R_INIT interrpu 00190H 00002H
@@R_INIT SPILCD 00192H 00000H
@@R_INIT systemin 00192H 00000H
@@R_INIT Remote 00192H 0000AH
@@R_INIT @rom 0019CH 00000H
@@CNST 0019CH 00360H CSEG UNITP
@@CNST @cstart 0019CH 00000H
@@CNST main 0019CH 00000H
@@CNST time0 0019CH 00000H
@@CNST interrpu 0019CH 00000H
@@CNST SPILCD 0019CH 00360H
@@CNST systemin 004FCH 00000H
@@CNST Remote 004FCH 00000H
@@LCODE 004FCH 00637H CSEG
@@LCODE @cstart 004FCH 00076H
@@LCODE @llsh 00572H 0001EH
@@LCODE @lsrsh 00590H 0001FH
@@LCODE @hdwinit 005AFH 00001H
@@LCODE exit 005B0H 00024H
@@LCODE vsprintf 005D4H 0055FH
@@CODE 00B33H 009D2H CSEG
@@CODE main 00B33H 0001DH
@@CODE time0 00B50H 00033H
@@CODE interrpu 00B83H 00044H
@@CODE SPILCD 00BC7H 007F2H
@@CODE systemin 013B9H 00016H
@@CODE Remote 013CFH 00136H
@@CALF 01505H 00000H CSEG
@@CALF @cstart 01505H 00000H
@@CALF main 01505H 00000H
@@CALF time0 01505H 00000H
@@CALF interrpu 01505H 00000H
@@CALF SPILCD 01505H 00000H
@@CALF systemin 01505H 00000H
@@CALF Remote 01505H 00000H
* gap * 01505H 06AFBH
MEMORY=BANK0
BASE ADDRESS=08000H SIZE=04000H
78K/0 Series Linker V3.80 Date:26 Oct 2007 Page: 3
OUTPUT INPUT INPUT BASE SIZE
SEGMENT SEGMENT MODULE ADDRESS
* gap * 08000H 04000H
MEMORY=IXRAM
BASE ADDRESS=0E000H SIZE=01800H
OUTPUT INPUT INPUT BASE SIZE
SEGMENT SEGMENT MODULE ADDRESS
* gap * 0E000H 01800H
MEMORY=LRAM
BASE ADDRESS=0FA00H SIZE=00020H
OUTPUT INPUT INPUT BASE SIZE
SEGMENT SEGMENT MODULE ADDRESS
* gap * 0FA00H 00020H
MEMORY=RAM
BASE ADDRESS=0FB00H SIZE=00500H
OUTPUT INPUT INPUT BASE SIZE
SEGMENT SEGMENT MODULE ADDRESS
@@DATA 0FB00H 0009CH DSEG UNITP
@@DATA @cstart 0FB00H 00078H
@@DATA main 0FB78H 00000H
@@DATA time0 0FB78H 00000H
@@DATA interrpu 0FB78H 00000H
@@DATA SPILCD 0FB78H 00024H
@@DATA systemin 0FB9CH 00000H
@@DATA Remote 0FB9CH 00000H
@@DATA @rom 0FB9CH 00000H
@@INIT 0FB9CH 0000CH DSEG UNITP
@@INIT @cstart 0FB9CH 00000H
@@INIT main 0FB9CH 00000H
@@INIT time0 0FB9CH 00000H
@@INIT interrpu 0FB9CH 00002H
@@INIT SPILCD 0FB9EH 00000H
@@INIT systemin 0FB9EH 00000H
@@INIT Remote 0FB9EH 0000AH
@@INIT @rom 0FBA8H 00000H
* gap * 0FBA8H 00278H
@@INIS 0FE20H 00000H DSEG SADDRP
@@INIS @cstart 0FE20H 00000H
@@INIS main 0FE20H 00000H
@@INIS time0 0FE20H 00000H
@@INIS interrpu 0FE20H 00000H
@@INIS SPILCD 0FE20H 00000H
@@INIS systemin 0FE20H 00000H
@@INIS Remote 0FE20H 00000H
@@INIS @rom 0FE20H 00000H
@@DATS 0FE20H 00000H DSEG SADDRP
@@DATS @cstart 0FE20H 00000H
@@DATS main 0FE20H 00000H
@@DATS time0 0FE20H 00000H
@@DATS interrpu 0FE20H 00000H
@@DATS SPILCD 0FE20H 00000H
@@DATS systemin 0FE20H 00000H
@@DATS Remote 0FE20H 00000H
@@DATS @rom 0FE20H 00000H
@@BITS 0FE20H 00000H BSEG
78K/0 Series Linker V3.80 Date:26 Oct 2007 Page: 4
@@BITS @cstart 0FE20H.0 00000H.0
@@BITS main 0FE20H.0 00000H.0
@@BITS time0 0FE20H.0 00000H.0
@@BITS interrpu 0FE20H.0 00000H.0
@@BITS SPILCD 0FE20H.0 00000H.0
@@BITS systemin 0FE20H.0 00000H.0
@@BITS Remote 0FE20H.0 00000H.0
* gap * 0FE20H 00098H
@@RTARG0 0FEB8H 00008H DSEG AT
@@RTARG0 @RTARG0 0FEB8H 00008H
* gap * 0FEC0H 00040H
* gap (Not Free Area) * 0FF00H 00100H
MEMORY=BANK1
BASE ADDRESS=18000H SIZE=04000H
OUTPUT INPUT INPUT BASE SIZE
SEGMENT SEGMENT MODULE ADDRESS
* gap * 18000H 04000H
MEMORY=BANK2
BASE ADDRESS=28000H SIZE=04000H
OUTPUT INPUT INPUT BASE SIZE
SEGMENT SEGMENT MODULE ADDRESS
* gap * 28000H 04000H
MEMORY=BANK3
BASE ADDRESS=38000H SIZE=04000H
OUTPUT INPUT INPUT BASE SIZE
SEGMENT SEGMENT MODULE ADDRESS
* gap * 38000H 04000H
MEMORY=BANK4
BASE ADDRESS=48000H SIZE=04000H
OUTPUT INPUT INPUT BASE SIZE
SEGMENT SEGMENT MODULE ADDRESS
* gap * 48000H 04000H
MEMORY=BANK5
BASE ADDRESS=58000H SIZE=04000H
OUTPUT INPUT INPUT BASE SIZE
SEGMENT SEGMENT MODULE ADDRESS
* gap * 58000H 04000H
Target chip : uPD78F0547_80
Device file : V2.00