www.pudn.com > rs3228v11tar.gz > wordmem.vhd, change:1998-10-01,size:3248b


-------------------------------------------------------------------------
-- model:     ENTITY wordmem, ARCHITECTURE rtl
-- copyright: Christian Schuler, GMD-FOKUS, 12/2/1998
--
--
-- description:
--   store of complete codeword for rs(32,28)-gf(256) decoder
--   FIFO and random access for error correction
--   generated by code generator genfec
--
-- modified:
--
-------------------------------------------------------------------------
LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
USE work.rs_pkg.ALL;

ENTITY wordmem IS
  PORT (
    clk     : IN    STD_ULOGIC;
    reset   : IN    STD_ULOGIC;
    fifo_we : IN    STD_ULOGIC;
    fifo_re : IN    STD_ULOGIC;
    ram_we  : IN    STD_ULOGIC;
    ram_re  : IN    STD_ULOGIC;
    fifo_in : IN    STD_ULOGIC_VECTOR(mm-1 DOWNTO 0);
    ram_in  : IN    STD_ULOGIC_VECTOR(mm-1 DOWNTO 0);
    addr_in : IN    STD_ULOGIC_VECTOR(addr_width-1 DOWNTO 0);
    d_out   : OUT   STD_ULOGIC_VECTOR(mm-1 DOWNTO 0));
END wordmem;

-------------------------------------------------------------------------

ARCHITECTURE rtl OF wordmem IS

  TYPE state_t IS (idle,fifo_write,fifo_read);
  SIGNAL state: state_t;

  SIGNAL addr_cnt   : INTEGER RANGE 0 TO nn-1;
  SIGNAL addr_bus   : STD_ULOGIC_VECTOR(addr_width-1 DOWNTO 0);
  SIGNAL data_bus   : STD_ULOGIC_VECTOR(mm-1 DOWNTO 0);

  SIGNAL sync_ram_we : STD_ULOGIC;

BEGIN

  -----------------------------------------------------------------------------
  addr_cnt_ctrl:
  PROCESS(clk)
  BEGIN
    IF clk'EVENT AND clk = '1' THEN
      IF reset = '1' THEN
        state <= idle;
        addr_cnt <= 0;
      ELSE        
        CASE state IS
          WHEN idle =>
            IF fifo_we = '1' THEN
              addr_cnt <= 1;
              state <= fifo_write;
            END IF;
            IF fifo_re = '1' THEN
              addr_cnt <= 1;
              state <= fifo_read;
            END IF;
          WHEN fifo_write =>            
            IF addr_cnt = nn-1 THEN
              addr_cnt <= 0;
              state <= idle;
            ELSIF fifo_we = '1' THEN
              addr_cnt <= addr_cnt + 1;
            END IF; 
          WHEN fifo_read =>
            
            IF addr_cnt = nn-1 THEN
              state <= idle;
              addr_cnt <= 0;
            ELSIF fifo_re = '1' THEN
              addr_cnt <= addr_cnt + 1;
            END IF;
 
        END CASE;
      END IF;
    END IF;         
  END PROCESS; 

  -----------------------------------------------------------------------------
  write_ctrl:
  PROCESS(fifo_we,ram_we)
  BEGIN
    sync_ram_we <= fifo_we OR ram_we;
  END PROCESS; 

  -------------------------------------------------------------------------
  bus_mux:
  PROCESS(ram_we,ram_re,ram_in,addr_in,fifo_in,addr_cnt)
  BEGIN
    IF ram_we = '1' OR ram_re = '1' THEN -- ram access priority
      addr_bus <= addr_in;
      data_bus <= ram_in;
    ELSE
      addr_bus <= int2suv(addr_cnt,addr_width);
      data_bus <= fifo_in;
    END IF;          
  END PROCESS;

  -------------------------------------------------------------------------
  ram: sram_word
    PORT MAP (
     di     => data_bus,
     a      => addr_bus,
     wr_en  => sync_ram_we,
     wr_clk => clk,
     do     => d_out);

END rtl; -- of wordmem