www.pudn.com > rs3228v11tar.gz > sram_synd.vhd, change:1998-10-01,size:1426b


-----------------------------------------------------------------
-- model:     ENTITY sram_synd , ARCHITECTURE rtl
-- copyright: Christian Schuler, GMD-FOKUS, 12/2/1998
--
--
-- description: 
--   synthesizable rtl model for synchronous XILINX RAM (XC4000EX/XL)
--   generated by code generator genfec
--
-- modified: 
--
-------------------------------------------------------------------------
LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;

USE work.rs_pkg.ALL;

-------------------------------------------------------------------------

ENTITY sram_synd IS
  PORT(
    di    : IN  STD_ULOGIC_VECTOR(mm-1 DOWNTO 0);
    a     : IN  STD_ULOGIC_VECTOR(synd_addr_w-1 DOWNTO 0);
    wr_en : IN  STD_ULOGIC;    
    wr_clk: IN  STD_ULOGIC;    
    do    : OUT STD_ULOGIC_VECTOR(mm-1 DOWNTO 0)
    );    
END sram_synd;

-------------------------------------------------------------------------

ARCHITECTURE rtl OF sram_synd IS

  CONSTANT addr_max: INTEGER := 2 ** synd_addr_w - 1;
  TYPE ram_t IS ARRAY (0 TO addr_max) OF STD_ULOGIC_VECTOR(mm-1 DOWNTO 0);
  SIGNAL memory: ram_t;

BEGIN

  PROCESS (wr_clk,a,memory)
    VARIABLE iaddr: INTEGER RANGE 0 TO addr_max;  
  BEGIN
    iaddr := suv2int(a);
    -- edge triggered write
    IF wr_clk'EVENT AND wr_clk = '1' THEN
      IF wr_en = '1' THEN
        memory(iaddr) <= di;   
      END IF;
    END IF;
    do <= memory(iaddr);   
  END PROCESS;
    
END rtl; -- of sram_synd