www.pudn.com > rs3228v11tar.gz > gfnorm.vhd, change:1998-10-01,size:3761b


-------------------------------------------------------------------------
-- model:     ENTITY gfnorm, ARCHITECTURE rtl
-- copyright: Christian Schuler, GMD-FOKUS, 12/2/1998
--
--
-- description: 
--   galois field 256 normalization
--   inversion with pipeline power function
--   generated by code generator genfec
--
-- modified: 
--
-------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

USE work.rs_pkg.ALL;

ENTITY gfnorm IS
  PORT (
    clk      : IN    STD_ULOGIC;
    reset    : IN    STD_ULOGIC;
    in_enb0  : IN    STD_ULOGIC;
    in_enb1  : IN    STD_ULOGIC;
    d_in     : IN    STD_ULOGIC_VECTOR(mm-1 DOWNTO 0);
    out_enb  : OUT   STD_ULOGIC;
    read_enb : OUT   STD_ULOGIC;
    d_out    : INOUT STD_ULOGIC_VECTOR(mm-1 DOWNTO 0));
END gfnorm;

-------------------------------------------------------------
ARCHITECTURE rtl OF gfnorm IS

  SIGNAL step_cnt : INTEGER RANGE 0 TO mm;
  SIGNAL p_result : STD_ULOGIC_VECTOR(mm-1 DOWNTO 0);
  SIGNAL inverse  : STD_ULOGIC_VECTOR(mm-1 DOWNTO 0);
  SIGNAL d_in_save: STD_ULOGIC_VECTOR(mm-1 DOWNTO 0);
  SIGNAL in_enb   : STD_ULOGIC;

  TYPE state_t IS (idle,inversion,normalization);
  SIGNAL state: state_t;

BEGIN

  in_enb <= in_enb0 OR in_enb1;
  ----------------------------------------------------------------------
  step_counter:
  PROCESS (clk)
  BEGIN
    IF clk'EVENT AND clk = '1' THEN
      IF reset = '1' THEN
        step_cnt <= 0;
      ELSE
        IF state = inversion THEN
          step_cnt <= step_cnt + 1;
        ELSE
          step_cnt <= 0;
        END IF;
      END IF;
    END IF;
  END PROCESS; 

  ----------------------------------------------------------------------
  main_fsm:
  PROCESS (clk)
  BEGIN
    IF clk'EVENT AND clk = '1' THEN
      IF reset = '1' THEN
        state <= idle;
        out_enb <= '0';
        read_enb <= '1'; -- indicates , that new data can be accepted
      ELSE
        CASE state IS
          WHEN idle =>
            out_enb <= '0';
            IF in_enb = '1' THEN
              state <= inversion;
              read_enb <= '0';       -- stop input for inversion process
            END IF;
          WHEN inversion =>
            IF step_cnt = mm-1 THEN
              state <= normalization;
              read_enb <= '1'; 
              out_enb <= '1';
            END IF;
          WHEN normalization =>
            IF in_enb /= '1' THEN -- prepare for restart
              state <= idle;
              out_enb <= '0';
            END IF;
        END CASE;
      END IF;
    END IF;
  END PROCESS; 

  ----------------------------------------------------------------------
  arithmetical_unit:
  PROCESS (clk)
    VARIABLE pp,m1,m2: STD_ULOGIC_VECTOR(mm-1 DOWNTO 0);
  BEGIN
    IF clk'EVENT AND clk = '1' THEN
      IF reset = '1' THEN
        d_out <= alpha_1;
      ELSE
        CASE state IS
          WHEN idle =>
            m1 := alpha_1;
            m2 := alpha_1;
            pp := alpha_1;
            IF in_enb = '1' THEN
              pp := d_in;
              d_in_save <= d_in;   -- save first input in  register
            END IF;
          WHEN inversion =>
            pp := p_result;
            IF step_cnt = mm-1 THEN  -- first inversion, should generate alpha_1
              m1 := d_in_save;
              m2 := d_out;         -- should contain inverse of first input
              inverse <= d_out;
            ELSE  
              m1 := p_result;
              m2 := d_out;
            END IF;
          WHEN normalization =>
            m1 := d_in;  
            m2 := inverse;
        END CASE;
        d_out <= gf256_mul(m1,m2);
        p_result <= gf256_pow2(pp);        
      END IF;
    END IF;

  END PROCESS; 



END rtl; -- OF gfnorm