www.pudn.com > Bit1611_demo_code.rar > VP.H
/* **********************************************************************
Copyright (c) 2002-2006 Beyond Innovation Technology Co., Ltd
All rights are reserved. Reproduction in whole or in parts is
prohibited without the prior written consent of the copyright owner.
----------------------------------------------------------------------
Module: VP.H - Video Processor.
Purpose: Interface of VP module.
Version: 0.01 08:33PM 2005/12/27
Compiler: Keil 8051 C Compiler v8.01
Reference:
[1] BIT1611B Data Sheet Version 1.0, 2005-11-10,
Beyond Innovation Technology
----------------------------------------------------------------------
Modification:
R0.01 08:33PM 2005/12/27 Jeffrey Chang
Reason:
1. Original.
Solution:
********************************************************************** */
#ifndef _VP_H_
#define _VP_H_
/* ------------------------------------
Header Files
------------------------------------ */
#include "eeprom.h"
#include "platform.h"
/* ------------------------------------
Macro Definitions
------------------------------------ */
#undef EXTERN
#ifdef _VP_C_
#define EXTERN
#else
#define EXTERN extern
#endif
/* ::::::::::::::::::::::::::::::::::::
VP Register Definitions
:::::::::::::::::::::::::::::::::::: */
// [1]11 $7.1 Hardware Version
#define VP_000_HW_VER 0x000 // [1]11 Hardware version
#define VP_MASK_HW_VER 0xC6 // 7 6 5 4 3 2 1 0
// | | | | | | |_|_ Product Version
// | | | |_|_|_____ Product Number
// |_|_|___________ Product Group
// 1 1 0 0 0 1 1 0 0xC6
#define VP_001_SW_VER 0x001 // [1]11 Softwre version
// [1]12 $7.2 Interrupt (FLAG, MASK and ACK)
#define VP_002_INT_FLAG 0x002 // [1]12 Interrupt Flag
#define VP_MASK_HASSIG_FLAG 0x01 // [1]12 Signal Ready by HSYNC Revised by JC 01:15PM 2006/02/10
#define VP_MASK_NOSIG_FLAG 0x02 // [1]12 No Signal by HSYNC
#define VP_MASK_MODE_FLAG 0x04 // [1]12 VSYNC changes
#define VP_MASK_VSYNC_FLAG 0x08 // [1]12 VSYNC falling edge
#define VP_MASK_ERROR1_FLAG 0x10 // [1]12 Timer 1 or Line Buffer Error 1 error
#define VP_MASK_ERROR2_FLAG 0x20 // [1]12 Timer 2 or Line Buffer Error 2 error
#define VP_MASK_IR_FLAG 0x40 // [1]12 IR Remote Control Detection
#define VP_MASK_KEY_FLAG 0x80 // [1]12 GPI Detection
#define VP_003_INT_MASK 0x003 // [1]12 Interrupt Mask
#define VP_MASK_HASSIG_MASK 0x01 // Signal Ready by HSYNC Revised by JC 01:15PM 2006/02/10
#define VP_MASK_NOSIG_MASK 0x02 // No Signal by HSYNC
#define VP_MASK_MODE_MASK 0x04 // VSYNC changes
#define VP_MASK_VSYNC_MASK 0x08 // VSYNC falling edge
#define VP_MASK_UNDER_MASK 0x10 // Timer 1 or Line Buffer Error 1 error
#define VP_MASK_OVER_MASK 0x20 // Timer 2 or Line Buffer Error 2 error
#define VP_MASK_IR_MASK 0x40 // IR Remote Control Detection
#define VP_MASK_KEY_MASK 0x80 // GPI Detection
#define VP_004_INT_ACK 0x004 // [1]13 Interrupt ACK
#define VP_MASK_HASSIG_ACK 0x01 // Signal Ready by HSYNC Revised by JC 01:15PM 2006/02/10
#define VP_MASK_NOSIG_ACK 0x02 // No Signal by HSYNC
#define VP_MASK_MODE_ACK 0x04 // VSYNC changes
#define VP_MASK_VSYNC_ACK 0x08 // VSYNC falling edge
#define VP_MASK_UNDER_ACK 0x10 // Timer 1 or Line Buffer Error 1 error
#define VP_MASK_OVER_ACK 0x20 // Timer 2 or Line Buffer Error 2 error
#define VP_MASK_IR_ACK 0x40 // IR Remote Control Detection
#define VP_MASK_KEY_ACK 0x80 // GPI Detection
#define VP_005_INT_ATTR 0x005 // [1]13 Interrupt Attribute
#define VP_MASK_INT_TYPE 0x01 // [1]13 0=Edge, 1=Level
#define VP_MASK_INT_POL 0x02 // [1]13 1=Low/Falling Active, 0=High/Rising Active
#define VP_MASK_ERROR_TYPE 0x04 // [1]13 0=ODD Field, 1=EVEN Field
#define VP_MASK_LOAD_IN 0x10 // [1]15 Double Buffer Load Enable
#define VP_MASK_LOAD_TYPE 0x20 // [1]15 Double Buffer Register Update Type
#define VP_MASK_INT_VSSEL 0x40 // [1]13 Interrupt Vecotr[3] source select
#define VP_MASK_INT_ERREL 0x80 // [1]13 Interrupt Vecotr[5:4] source select
// [1]19 $7.4 Pad Type Setup
#define VP_007_PORT_ATTR 0x007 // [1]19 Port Attribute
#define VP_MASK_ROUT_TRI 0x01 // [1]19 ROUT Port Tri-state enable
#define VP_MASK_GOUT_TRI 0x02 // [1]19 GOUT Port Tri-state enable
#define VP_MASK_BOUT_TRI 0x04 // [1]19 BOUT Port Tri-state enable
#define VP_MASK_OCLK_TRI 0x08 // [1]19 OCLK Pin Tri-state enable
#define VP_MASK_ODE_TRI 0x10 // [1]19 ODE Pin Tri-state enable
#define VP_MASK_INT_TRI 0x20 // [1]19 INT Pin Tri-state enable
// [1]20 $7.5 GPO Function
#define VP_008_GPO_SEL 0x008 // [1]20 GPO Enable 0=Disable, 1=Enable
#define VP_009_GPO_TYPE 0x009 // [1]20 GPO Type 0=Normal, 1=Tri-State
#define VP_MASK_GPO_TYPE 0x3F // [1]20 GPO Type
#define VP_MASK_REGS_CLKEN 0x80 // ???
#define VP_00A_GPO_REG 0x00A // [1]20 GPO Value 0=Low Level, 1=High Level
// [1]23 $7.6.2 Software Reset
#define VP_00B_SRST_ATTR1 0x00B // [1]23 Software Reset
#define VP_MASK_SYNCDET_EN 0x01 // [1]23 SYNCDET Software Reset
#define VP_MASK_PWM1_EN 0x02 // [1]23 PWM1 Software Reset
#define VP_MASK_PWM2_EN 0x04 // [1]23 PWM2 Software Reset
#define VP_MASK_PWM3_EN 0x08 // [1]23 PWM3 Software Reset
#define VP_MASK_PWM4_EN 0x10 // [1]23 PWM4 Software Reset
#define VP_MASK_SAMPLE_EN 0x20 // [1]23 SAMPLE Software Reset
#define VP_MASK_OSD_CLKEN 0x40 // ???
#define VP_MASK_PLL_SRC 0x80 // [1]76 PLL base clock select
#define VP_00C_SRST_ATTR2 0x00C // [1]23 Software Reset
#define VP_MASK_SRST_VP 0x01 // [1]23 PWM Software Reset
#define VP_MASK_SRST_OUT 0x02 // [1]23 Power Software Reset
#define VP_MASK_SRST_OSD 0x04 // [1]23 OSD Software Reset
#define VP_MASK_SRST_CHROMA 0x08 // [1]23 Chroma Software Reset
#define VP_MASK_SRST_SYNC 0x10 // [1]23 SYNC Software Reset
#define VP_MASK_SRST_CLOCK 0x20 // [1]23 Clock Software Reset
#define VP_MASK_SRST_AGC 0x40 // [1]23 AGC Software Reset
#define VP_MASK_SRST_COMB 0x80 // [1]23 Comb Filter Software Reset
// [1]25 $7.7 Built-in DAC
#define VP_00E_CLK_ATTR1 0x00E // [1]25
#define VP_MASK_XCLK_SEL 0x03 // [1]26 XCLK Clock Domain Source Select
#define VP_MASK_DACCLK_MODE 0x0C // [1]25 DAC Clock Phase Select
#define VP_MASK_DAC_POL 0x10 // [1]25 DAC LCLK Source polarity
#define VP_MASK_DAC_SEL 0x20 // [1]25 DAC Clock polarity
#define VP_MASK_DAC_DG 0x40 // [1]25 DAC Noise Reduce
#define VP_MASK_DAC_EN 0x80 // [1]25 DAC Enable
// [1]26 $7.8 Clock Domain Systems
#define VP_00F_CLK_ATTR2 0x00F // [1]26
#define VP_MASK_LCLK_EN 0x01 // [1]26 LCLK Enable: 0=Disable, 1=Enable
#define VP_MASK_LCLK_POL 0x02 // [1]26 LCLK Domain Polarity
#define VP_MASK_LCLK_SEL 0x0C // [1]26 CLK Domain Clock Source Select
#define VP_MASK_PCLK_EN 0x10 // [1]26 PCLK Domain Enable: 0=Disable, 1=Enable
#define VP_MASK_PCLK_POL 0x20 // [1]26 PCLK Domain Polarity: 0=Normal, 1=Invert
#define VP_MASK_PCLK_SEL 0x40 // [1]26 PCLK Domain Clock Source Select
#define VP_MASK_DELTA_MODE 0x80 // ???
// [1]28 $7.9 Panel Timing
#define VP_010013_HSYNC_PULSE_WIDTH 0x010 // [1]28 PANEL HSYNC Pulse Width
#define VP_011013_H_ACTIVE_START 0x011 // [1]28 PANEL Active Window Horizontal Start Position
#define VP_012013_H_ACTIVE_END 0x012 // [1]28 PANEL Active Window Horizontal End Position
#define VP_013_PANEL_H_ATTR 0x013
#define VP_MASK_H_ACTIVE_END_MSB 0x03 // [1]28
#define VP_MASK_H_ACTIVE_START_MSB 0x0C // [1]28
#define VP_MASK_HSYNC_PULSE_WIDTH_MSB 0x30 // [1]28
#define VP_MASK_SYNCO_EN 0x40 // [1]33 Sync with input VSYNC
#define VP_MASK_SYNCO_MODE 0x80 // [1]33 Two-Field Synchronization mode select
#define VP_014016_H_TOTAL_LENGTH_EVEN_M0 0x014 // [1]28 PANEL EVEN Field Horizontal Total Length
#define VP_015016_H_TOTAL_LENGTH_ODD_M0 0x015 // [1]28 PANEL ODD Field Horizontal Total Length
#define VP_016_H_TOTAL_LENGTH_M0 0x016
#define VP_MASK_H_TOTAL_LENGTH_ODD_M0_MSB 0x03 // [1]28
#define VP_MASK_H_TOTAL_LENGTH_EVEN_M0_MSB 0x30 // [1]28
// [1]59 $7.29 Timing Adjustment
#define VP_017019_DELAY_OCLK_M0_EVEN 0x017 // [1]59 Even Field outputs VS delay in OCLK
#define VP_018019_DELAY_OCLK_M0_ODD 0x018 // [1]59 Odd Field outputs VS delay in OCLK
// [1]28 $7.9 Panel Timing
#define VP_01A01C_H_TOTAL_LENGTH_EVEN_M1 0x01A // [1]28 PANEL EVEN Field Horizontal Total Length
#define VP_01B01C_H_TOTAL_LENGTH_ODD_M1 0x01B // [1]28 PANEL ODD Field Horizontal Total Length
#define VP_01C_H_TOTAL_LENGTH_M1 0x01C
#define VP_MASK_H_TOTAL_LENGTH_ODD_M1_MSB 0x03 // [1]28
#define VP_MASK_H_TOTAL_LENGTH_EVEN_M1_MSB 0x30 // [1]28
// [1]59 $7.29 Timing Adjustment
#define VP_01D01F_DELAY_OCLK_M1_EVEN 0x01D // [1]59 Even Field outputs VS delay in OCLK
#define VP_01E01F_DELAY_OCLK_M1_ODD 0x01E // [1]59 Odd Field outputs VS delay in OCLK
// [1]28 $7.9 Panel Timing
#define VP_020_VSYNC_PULSE_WIDTH 0x020 // [1]28 PANEL VSYNC Pulse Width
#define VP_021_V_ACTIVE_START 0x021 // [1]28 PANEL Active Window Vertical Start Position
#define VP_022024_V_ACTIVE_END 0x022 // [1]28 PANEL Active Window Vertical End Position
#define VP_023024_V_TOTAL_LENGTH 0x023 // [1]28 PANEL Vertical Total Length
// [1]29 $7.10 Output Data Path
#define VP_024_OUTPUT_DATAPATH 0x024 // [1]29 OUTPUT data path
#define VP_MASK_V_TOTAL_LENGTH 0x01 // [1]28 PANEL Vertical Total Length MSB
#define VP_MASK_V_ACTIVE_END 0x02 // [1]28 PANEL Active Window Vertical End Position MSB
#define VP_MASK_SWAPE_ORB 0x04 // [1]29 R EVEN Data bus swap B Data bus 0=Disable, 1=Enable
#define VP_MASK_SWAPE_ORG 0x08 // [1]29 R EVEN Data bus swap G Data bus 0=Disable, 1=Enable
#define VP_MASK_SWAPE_OGB 0x10 // [1]29 R EVEN Data bus swap G Data bus 0=Disable, 1=Enable
#define VP_MASK_SWAPO_ORB 0x20 // [1]29 R ODD Data bus swap B Data bus 0=Disable, 1=Enable
#define VP_MASK_SWAPO_ORG 0x40 // [1]29 R ODD Data bus swap G Data bus 0=Disable, 1=Enable
#define VP_MASK_SWAPO_OGB 0x80 // [1]29 R ODD Data bus swap G Data bus 0=Disable, 1=Enable
#define VP_MASK_ACTIVE_TOTAL (VP_MASK_V_ACTIVE_END | VP_MASK_V_TOTAL_LENGTH)
// [1]29 $7.10 Output Data Path
#define VP_025_OUTPUT_ATTR 0x025 // [1]29 OUTPUT data path
#define VP_MASK_ROUT_POL 0x01 // [1]29 R Data output Polarity 0=Normal, 1=Invert
#define VP_MASK_GOUT_POL 0x02 // [1]29 G Data output Polarity 0=Normal, 1=Invert
#define VP_MASK_BOUT_POL 0x04 // [1]29 B Data output Polarity 0=Normal, 1=Invert
#define VP_MASK_SERIAL_OUT 0x08 // [1]31 Output Clock Polarity 0=Normal, 1=Invert
#define VP_MASK_ROUT_ROT 0x10 // [1]29 R Data Rotate 0=Disable, 1=Invert
#define VP_MASK_GOUT_ROT 0x20 // [1]29 G Data Rotate 0=Disable, 1=Invert
#define VP_MASK_BOUT_ROT 0x40 // [1]29 B Data Rotate 0=Disable, 1=Invert
#define VP_MASK_OCLK_POL 0x80 // [1]29 Output Clock Polarity
// [1]32 $7.12 Special Output Setup
#define VP_026_SPECIAL_OUTPUT 0x026 // [1]32
#define VP_MASK_RTS1 0x07 // [1]32 RTS1 Selection
#define VP_MASK_RTS2 0x70 // [1]32 RTS2 Selection
#define VP_MASK_SWAP_SRC 0x08 // ???
#define VP_MASK_PROTECT_MODE 0x80 // [1]33 Miinimum Output Lines protect
// [1]34 $7.14 TCON Function
#define VP_027029_STV_START 0x027 // [1]34 STV Signal Start[7:0]
#define VP_028029_STV_END 0x028 // [1]34 STV Signal End[7:0]
#define VP_029_STV_ATTR 0x029 // [1]34 STV Attribute
#define VP_MASK_STV_START_MSB 0x01 // [1]34 STV Signal Start[8]
#define VP_MASK_STV_END_MSB 0x02 // [1]34 STV Signal End[8]
#define VP_MASK_VCOM_TYPE 0x0C // [1]34 VCOM Signal TYPE
#define VP_MASK_FRP_POL 0x10 // [1]34 FRP Output Polarity
#define VP_MASK_CPH_HALF 0x20 // [1]36 TCON Clock Output Mode
#define VP_MASK_3CLK_SEL 0x40 // [1]36 Clock Type Select
#define VP_MASK_CPH_MODE 0x80 // [1]36 CPH Clcok Mode
#define VP_02A02E_STH_START 0x02A // [1]34 STH Signal Start[7:0]
#define VP_02B02E_STH_END 0x02B // [1]34 STH Signal End[7:0]
#define VP_02C02E_CKV_START 0x02C // [1]34 CKV Signal Start[7:0]
#define VP_02D02E_CKV_END 0x02D // [1]34 CKV Signal End[7:0]
#define VP_02F033_LD_START 0x02F // [1]34 LD Signal Start[7:0]
#define VP_030033_LD_END 0x030 // [1]34 LD Signal End[7:0]
#define VP_031033_OEH_START 0x031 // [1]34 OEH Signal Start[7:0]
#define VP_032033_OEH_END 0x032 // [1]34 OEH Signal End[7:0]
#define VP_033_LD_OEH_ATTR 0x033 // [1]34 LD/OEH Attribute
#define VP_MASK_OEH_START_MSB 0x03 // [1]34 OEH Signal Start
#define VP_MASK_OEH_END_MSB 0x0C // [1]34 OEH Signal End
#define VP_MASK_LD_START_MSB 0x30 // [1]34 LD Signal Start
#define VP_MASK_LD_END_MSB 0xC0 // [1]34 LD Signal End
#define VP_034035_VCOM_SHIFT 0x034 // [1]34 VCOM Shift
#define VP_035_TCON_ATTR1 0x035 // [1]34 TCON Attribute 1
#define VP_MASK_VCOM_SHIFT_MSB 0x03 // [1]34 VCOM Shift[9:8]
#define VP_MASK_BUS_INV 0x0C // [1]34 Data Bus Control
#define VP_MASK_CPH3_PHASE 0x70 // [1]37 CPH3 clock delay phase
#define VP_MASK_CPH3_POL 0x80 // [1]37 CPH3 clock polarity
#define VP_036_TCON_GPO 0x036 // [1]34 TCON GPO
#define VP_MASK_OEH_POL 0x01 // [1]34 OEH Output Polarity
#define VP_MASK_STH_POL 0x02 // [1]34 STH Output Polarity
#define VP_MASK_STV_POL 0x04 // [1]34 STV Output Polarity
#define VP_MASK_TCON_GPO 0x38 // [1]34 TCON GPO
#define VP_MASK_OEH_GATE 0x40 // [1]35 OEH gated with ODE
#define VP_MASK_LTPS_MODE 0x80 // [1]35 LTPS Mode select
#define VP_037_TCON_ATTR2 0x037 // [1]35 TCON Attribute 2
#define VP_MASK_STH_SEL 0x01 // [1]35 STH Output Selection
#define VP_MASK_STV_SEL 0x02 // [1]35 STV Output Selection
#define VP_MASK_TCON_RL 0x04 // [1]35 TCON R/L
#define VP_MASK_TCON_UD 0x08 // [1]35 TCON U/D
#define VP_MASK_Q2H_POL 0x10 // [1]35 Q2H Output Polarity
#define VP_MASK_LD_POL 0x20 // [1]35 LD Output Polarity
#define VP_MASK_CKV_POL 0x40 // [1]35 CKV Output Polarity
#define VP_MASK_TCON_EN 0x80 // [1]35 TCON Enable
#define VP_MASK_TCON_UD_RL (VP_MASK_TCON_RL | VP_MASK_TCON_UD)
#define VP_MASK_TCON_Q2H_UD_RL (VP_MASK_Q2H_POL | VP_MASK_TCON_RL | VP_MASK_TCON_UD)
#define VP_MASK_TCON_Q2H_UD_RL_STV_STH (VP_MASK_Q2H_POL | VP_MASK_TCON_RL | VP_MASK_TCON_UD | VP_MASK_STV_SEL | VP_MASK_STH_SEL)
#define VP_038_TCON_ATTR3 0x038 // [1]36 TCON Attribute 3
#define VP_MASK_CPH1_PHASE 0x07 // [1]36 CPH1 clock delay phase
#define VP_MASK_CPH1_POL 0x08 // [1]36 CPH1 clock polarity
#define VP_MASK_CPH2_PHASE 0x70 // [1]36 CPH2 clock delay phase
#define VP_MASK_CPH2_POL 0x80 // [1]37 CPH2 clock polarity
#define VP_039_TCON_ATTR4 0x039 // [1]37 TCON Attribute 4
#define VP_MASK_CPH1_SEL_M0 0x03 // [1]37 CPH1 Source Select for Even Field
#define VP_MASK_CPH2_SEL_M0 0x0C // [1]37 CPH2 Source Select for Even Field
#define VP_MASK_CPH3_SEL_M0 0x30 // [1]37 CPH3 Source Select for Even Field
#define VP_MASK_CPH1_EN 0x40 // [1]37 CPH1 output enable
#define VP_MASK_TCON_SYNC 0x80 // [1]38 STH,STV,UD and Q2H synchronize with VS
#define VP_03A_TCON_ATTR5 0x03A // [1]37 TCON Attribute 5
#define VP_MASK_CPH1_SEL_M1 0x03 // [1]37 CPH1 Source Select for Odd Field
#define VP_MASK_CPH2_SEL_M1 0x0C // [1]37 CPH2 Source Select for Odd Field
#define VP_MASK_CPH3_SEL_M1 0x30 // [1]37 CPH3 Source Select for Odd Field
#define VP_MASK_CPH2_EN 0x40 // [1]37 CPH2 output enable
#define VP_MASK_CPH3_EN 0x80 // [1]37 CPH3 output enable
// [1]41 $7.18 Background 2
#define VP_03B_TESTPAT2_ATTR 0x03B // [1]41
#define VP_MASK_BG2_G 0x03 // [1]41 Background 2
#define VP_MASK_BG2_B 0x0C // [1]41 Background 2
#define VP_MASK_BG2_R 0x30 // [1]41 Background 2
// [1]42 $7.19 Background and Test Pattern
#define VP_03C_TESTPAT_R 0x03C // [1]42 Test Pattern RED Color
#define VP_03D_TESTPAT_G 0x03D // [1]42 Test Pattern GREEN Color
#define VP_03E_TESTPAT_B 0x03E // [1]42 Test Pattern BLUE Color
#define VP_03F_TESTPAT_RATIO 0x03F // [1]42 Test Pattern Ratio
#define VP_040_TESTPAT_ATTR 0x040 // [1]42 Test Pattern Attribute
#define VP_MASK_PATTERN_TYPE 0x07 // Test Pattern Type
#define VP_MASK_PATTERN_HV 0x10 // Test Pattern HV
#define VP_MASK_PATTERN_DIR 0x20 // Test Pattern Direction
#define VP_MASK_BACKGROUND_EN 0x40 // Background Mode Enable 0=Disable, 1=Enable
#define VP_MASK_FREERUN_EN 0x80 // Free-Run Mode Enable
#define VP_MASK_PATTERN_TYPE_4096 0x00 // [1]23 Pure 4096 Color Pattern
#define VP_MASK_PATTERN_TYPE_RAMP_R 0x01 // [1]23 Ramp R Color Pattern
#define VP_MASK_PATTERN_TYPE_RAMP_G 0x02 // [1]23 Ramp G Color Pattern
#define VP_MASK_PATTERN_TYPE_RAMP_GR 0x03 // [1]23 Ramp G+R Color Pattern
#define VP_MASK_PATTERN_TYPE_RAMP_B 0x04 // [1]23 Ramp B Color Pattern
#define VP_MASK_PATTERN_TYPE_RAMP_BR 0x05 // [1]23 Ramp B +R Color Pattern
#define VP_MASK_PATTERN_TYPE_RAMP_BG 0x06 // [1]23 Ramp B+G Color Pattern
#define VP_MASK_PATTERN_TYPE_RAMP_BGR 0x07 // [1]23 Ramp B+G+R Color Pattern
#define VP_FREERUN_ON VP_MASK_FREERUN_EN
#define VP_FREERUN_OFF 0x00
// [1]43 $7.20 Auto Blue Screen
#define VP_041_AUTOON 0x041 // [1]43 Auto ON
#define VP_MASK_AUTOON_TIME 0x7F
#define VP_MASK_AUTOON_EN 0x80
// [1]44 $7.21 Input Image Windows Setup
#define VP_042044_INPUT_H_START_M0 0x042 // [1]44 Input Window Horizontal Start Position Mode 0
#define VP_043044_INPUT_H_END_M0 0x043 // [1]44 Input Window Horizontal End Position Mode 0
#define VP_044_INPUT_H_M0 0x044 // [1]44 Input Window Horizontal Mode 0
#define VP_MASK_INPUT_H_START_M0_MSB 0x07
#define VP_MASK_INPUT_H_END_M0_MSB 0x70
#define VP_045047_INPUT_V_START_M0 0x045 // [1]44 Input Window Vertical Start Position Mode 0
#define VP_046047_INPUT_V_END_M0 0x046 // [1]44 Input Window Vertical End Position Mode 0
#define VP_047_INPUT_V_M0 0x047 // [1]44 Input Window Vertical Mode 0
#define VP_MASK_INPUT_V_START_M0_MSB 0x07
#define VP_MASK_INPUT_V_END_M0_MSB 0x70
#define VP_04804A_INPUT_H_START_M1 0x048 // [1]44 Input Window Horizontal Start Position Mode 1
#define VP_04904A_INPUT_H_END_M1 0x049 // [1]44 Input Window Horizontal End Position Mode 1
#define VP_04A_INPUT_H_M1 0x04A // [1]44 Input Window Horizontal
#define VP_MASK_INPUT_H_START_M1_MSB 0x07
#define VP_MASK_INPUT_H_END_M1_MSB 0x70
#define VP_04B04D_INPUT_V_START_M1 0x04B // [1]44 Input Window Vertical Start Position Mode 1
#define VP_04C04D_INPUT_V_END_M1 0x04C // [1]44 Input Window Vertical End Position Mode 1
#define VP_04D_INPUT_V_M1 0x04D // [1]44 Input Window Vertical Mode 1
#define VP_MASK_INPUT_V_START_M1_MSB 0x07
#define VP_MASK_INPUT_V_END_M1_MSB 0x70
// [1]45 $7.22 Input Data Path
#define VP_04E_INPUT_DATAPATH 0x04E // [1]45 Input Data Path
#define VP_MASK_RIN_POL 0x01 // [1]45 R Data Input Polarity
#define VP_MASK_GIN_POL 0x02 // [1]45 G Data Input Polarity
#define VP_MASK_BIN_POL 0x04 // [1]45 B Data Input Polarity
#define VP_MASK_RIN_ROT 0x08 // [1]45 R Data Rotate
#define VP_MASK_GIN_ROT 0x10 // [1]45 G Data Rotate
#define VP_MASK_BIN_ROT 0x20 // [1]45 B Data Rotate
#define VP_MASK_AUTO_SWITCH 0x40 // [1]53 Auto Switch Mode
#define VP_MASK_SWITCH_MODE 0x80 // [1]53 Switch Mode (0=Mode0, 1=Mode1)
#define VP_04F_INPUT_ATTR 0x04F // [1]45 Input Data Path Attribute
#define VP_MASK_ISWAP_RB 0x01 // [1]45 Swap R/B Data Bus
#define VP_MASK_ISWAP_RG 0x02 // [1]45 Swap R/B Data Bus
#define VP_MASK_ISWAP_GB 0x04 // [1]45 Swap G/B Data Bus
#define VP_MASK_RIN_EN 0x10 // [1]45 R Data Input Port Enable
#define VP_MASK_GIN_EN 0x20 // [1]45 G Data Input Port Enable
#define VP_MASK_BIN_EN 0x40 // [1]45 B Data Input Port Enable
// [1]49 $7.24 Input Mode Selection
#define VP_050_INPUT_MODE 0x050
#define VP_MASK_IMODE 0x01 // [1]49 Input Mode Select
#define VP_MASK_SRC_SEL 0x06 // [1]49 Source Select
#define VP_MASK_PIXEL_MODE 0x18 // [1]49 Input Active Pixel Mode
#define VP_MASK_MCLK_MODE 0xE0 // [1]27 MCLK Domain Clock source select
#define VP_051_INPUT_MODE_POLARITY 0x051
#define VP_MASK_SORT_656 0x07 // [1]49 Data sequence Control
#define VP_MASK_IHS_POL 0x08 // [1]50 External HS polarity
#define VP_MASK_VHS_POL 0x10 // [1]50 External VS polarity
#define VP_MASK_EXT_SYNC 0x60 // [1]50 External Sync Enable
#define VP_052_INPUT_MODE_ATTR 0x052
#define VP_MASK_EVEN_SEL 0x03 // [1]50 EVEN/ODD Signal Select
#define VP_MASK_VISUAL_TYPE 0x04 // [1]50 Visual EVEN/ODD Mode
#define VP_MASK_SHIFT_EN 0x08 // [1]50 One Line Shift Enable
#define VP_MASK_SHIFT_BASE 0x10 // [1]50 One Line Shift Base
#define VP_MASK_CSYNC_SEL 0x20 // [1]52 CSYNC Select
#define VP_MASK_CSYNC_HS 0x40 // [1]52 CSYNC Decoder HSYNC output polarity
#define VP_MASK_CSYNC_VS 0x80 // [1]52 CSYNC Decoder VSYNC output polarity
// [1]54 $7.27 Display Window
#define VP_053_DISPLAY_V_START 0x053 // [1]54 Display Window Vertical Start Position
#define VP_054059_DISPLAY_V_END 0x054 // [1]54 Display Window Vertical End Position
#define VP_055059_DISPLAY_V_HEIGHT 0x055 // [1]54 Display Window Vertical Height
#define VP_056059_DISPLAY_H_START 0x056 // [1]54 Display Window Horizontal Start Position
#define VP_057059_DISPLAY_H_END 0x057 // [1]54 Display Window Horizontal End Position
#define VP_058059_DISPLAY_H_WIDTH 0x058 // [1]54 Display Window Horizontal Width
#define VP_059_DISPLAY_ATTR 0x059 // [1]54 Display Window Attribute
#define VP_MASK_DISPLAY_H_WIDTH_MSB 0x01
#define VP_MASK_DISPLAY_V_HEIGHT_MSB 0x02
#define VP_MASK_DISPLAY_V_END_MSB 0x04
#define VP_MASK_DISPLAY_H_START_MSB 0x30
#define VP_MASK_DISPLAY_H_END_MSB 0xC0
// [1]56 $7.28.1 Horizontal Scale Down (HSD)
#define VP_05A05C_HSD_START_P1 0x05A // [1]56 HSD Start Phase 1
#define VP_05B05C_HSD_START_P2 0x05B // [1]56 HSD Start Phase 2
#define VP_05C_HSD_START_MSB 0x05C // [1]56 HSD
#define VP_MASK_HSD_START_P1_MSB 0x0F
#define VP_MASK_HSD_START_P2_MSB 0xF0
#define VP_05D05F_HSD1_SHIFT 0x05D // [1]56 HSD Zone 1 Shift
#define VP_05E05F_HSD1_FIX 0x05E // [1]56 HSD Zone 1 Fix
#define VP_05F_HSD1_MSB 0x05F // [1]56 HSD
#define VP_MASK_HSD1_SHIFT_MSB 0x07
#define VP_MASK_HSD1_FIX_MSB 0x30
#define VP_060_HSD_ATTR 0x060 // [1]56 HSD Attribute
#define VP_MASK_HSD_EN 0x01 // [1]56 HSD Enable
#define VP_MASK_HSD_FILTER_EN 0x06 // [1]56 Filter Type
#define VP_MASK_SHAKE_MODE 0x08 // [1]56 Shake Mode
#define VP_MASK_WIDESCREEN_EN 0x40 // [1]56 Wide Screen Mode Enable
#define VP_MASK_WIDESCREEN_TYPE 0x80 // [1]56 Wide Screen Type
#define VP_061067_HSD2_SHIFT 0x061 // [1]56 HSD Zone 2 Shift
#define VP_062067_HSD2_FIX 0x062 // [1]56 HSD Zone 2 Fix
#define VP_063067_HSD3_SHIFT 0x063 // [1]56 HSD Zone 3 Shift
#define VP_064067_HSD3_FIX 0x064 // [1]56 HSD Zone 3 Fix
#define VP_065067_ANZOOM_R1 0x065 // [1]56 Nonlinear Increase Value
#define VP_066067_ANZOOM_R2 0x066 // [1]56 Nonlinear Decrease Value
#define VP_067_ANZOOM_ATTR 0x067 // [1]56 HSD Attribute
// [1]57 $7.28.2 Vertical Scale Down (VSD)
#define VP_06806A_VSD_START_EVEN_M0 0x068 // [1]57 VSD EVEN Field Start
#define VP_06906A_VSD_START_ODD_M0 0x069 // [1]57 VSD ODD Field Start
#define VP_06B06D_VSD_SHIFT_M0 0x06B // [1]57 VSD Shift
#define VP_06C06D_VSD_FIX_M0 0x06C // [1]57 VSD Fix
#define VP_06D_VSD_ATTR_M0 0x06D // [1]57 VSD Attribute
#define VP_MASK_VSD_EN_M0 0x01 // [1]57 VSD Enable
#define VP_MASK_VSD_FILTER_EN_M0 0x06 // [1]57 VSD Filter Enable
#define VP_MASK_CUT_AUTO_M0 0x08 // [1]57
#define VP_MASK_VSD_SHIFT_MSB_M0 0x10 // [1]57
#define VP_MASK_LINE_CUT_M0 0x20 // [1]57
#define VP_MASK_VSD_FIX_MSB_M0 0x40 // [1]57
#define VP_MASK_CUT_MODE_M0 0x80 // [1]57
// [1]59 $7.29 Timing Adjustment
#define VP_06E070_DELAY_IHS_EVEN_M0 0x06E // [1]59 Even Field outputs VS delay in IHS
#define VP_06F070_DELAY_IHS_ODD_M0 0x06F // [1]59 Odd Field outputs VS delay in IHS
#define VP_070_DELAY_IHS_M0 0x070 // [1]59 VS delay
#define VP_MASK_DELAY_IHS_ODD_M0_MSB 0x03
#define VP_MASK_DELAY_IHS_EVEN_M0_MSB 0x30
// [1]57 $7.28.2 Vertical Scale Down (VSD)
#define VP_071073_VSD_START_EVEN_M1 0x071 // [1]57 VSD EVEN Field Start
#define VP_072073_VSD_START_ODD_M1 0x072 // [1]58 VSD ODD Field Start
#define VP_074076_VSD_SHIFT_M1 0x074 // [1]58 VSD Shift
#define VP_075076_VSD_FIX_M1 0x075 // [1]58 VSD Fix
#define VP_076_VSD_ATTR_M1 0x076 // [1]58 VSD Attribute
#define VP_MASK_VSD_EN_M1 0x01 // [1]58 VSD Enable
#define VP_MASK_VSD_FILTER_EN_M1 0x06 // [1]58 VSD Filter Enable
#define VP_MASK_CUT_AUTO_M1 0x08
#define VP_MASK_VSD_SHIFT_MSB_M1 0x10
#define VP_MASK_LINE_CUT_M1 0x20
#define VP_MASK_VSD_FIX_MSB_M1 0x40
#define VP_MASK_CUT_MODE_M1 0x80
// [1]59 $7.29 Timing Adjustment
#define VP_077079_DELAY_IHS_EVEN_M1 0x077 // [1]59 Even Field outputs VS delay in IHS
#define VP_078079_DELAY_IHS_ODD_M1 0x078 // [1]59 Odd Field outputs VS delay in IHS
#define VP_079_DELAY_IHS_M1 0x079 // [1]59 VS delay
#define VP_MASK_DELAY_IHS_ODD_M1_MSB 0x03
#define VP_MASK_DELAY_IHS_EVEN_M1_MSB 0x30
#define VP_07B_RGBOUT_DLYO 0x07B // RGB odd field out delay
// [1]63 $7.30 Brightness/Contrast Adjustment
#define VP_07C_BRIGHTNESS_R 0x07C // [1]63 R Brightness
#define VP_07D_BRIGHTNESS_G 0x07D // [1]63 G Brightness
#define VP_07E_BRIGHTNESS_B 0x07E // [1]63 B Brightness
#define VP_07F_CONTRAST_R 0x07F // [1]63 R Contrast
#define VP_080_CONTRAST_G 0x080 // [1]63 G Contrast
#define VP_081_CONTRAST_B 0x081 // [1]63 B Contrast
// [1]65 $7.31 Image Enhancement
#define VP_082_BLACK_LEVEL 0x082 // [1]65
#define VP_083_WHITE_SLOPE 0x083
#define VP_084_BLACK_SLOPE 0x084
#define VP_085_WHITE_START 0x085
#define VP_086_BLACK_START 0x086
// [1]68 $7.31.3 UV Domain Process
#define VP_087_U_GAIN 0x087 // [1]68
#define VP_088_V_GAIN 0x088
// [1]69 $7.31.4 Chroma Transient Improvement (CTI)
#define VP_089_CTI_ATTR 0x089
#define VP_MASK_CTI_EN 0x01 // [1]69 CTI Enable
#define VP_MASK_CTI_BW 0x06 // [1]69 CTI Bandwidth Select
#define VP_MASK_CTI_COMP 0x18 // [1]69 CTI Compare Select
#define VP_MASK_CTI_GAIN 0xE0 // [1]69 CTI Gain Value
// [1]75 $7.34 Color Space Conversion
#define VP_08A_CTI_CORING 0x08A
#define VP_MASK_CTI_CORING 0x0F // [1]69 CTI Coring Value
#define VP_MASK_Y2R_SEL 0x10 // [1]75 Color Space Conversion
#define VP_MASK_BRIGHTNESS_SEL 0x20 // [1]63 Brightness Type Select
#define VP_MASK_ZERO1_EN 0x40 // [1]41 Blank enable before image process
#define VP_MASK_ZERO2_EN 0x80 // [1]41 Blank enable after image process
// [1]67 $7.31.2 Image Enhancement
#define VP_08B_IMAGE_ATTR 0x08B // Image Enhancement
#define VP_MASK_HUE_EN 0x01 // [1]68 HUE Enable
#define VP_MASK_CONTRAST_TYPE 0x02 // [1]63 Contrast Type
#define VP_MASK_COLOR_KILL 0x04 // [1]68 Color kill Enable
#define VP_MASK_DITHER_EN 0x08 // [1]74 Dither Enable
#define VP_MASK_FILTER_TYPE 0x70 // [1]67 YUV Domain Image Filter Type
#define VP_MASK_FILTER_EN 0x80 // [1]67 YUV Domain Image Enhance Enable
// [1]74 $7.33 Dither
#define VP_08C_DITHER_EVEN 0x08C // [1]74 EVEN Field Dither Factor
#define VP_08D_DITHER_ODD 0x08D // [1]74 Odd Field Dither Factor
// [1]68 $7.31.3 UV Domain Process
#define VP_08E_HUE_COS 0x08E // [1]68 Hue COS
#define VP_08F_HUE_SIN 0x08F // [1]68 Hue SIN
#define VP_090_U_MAX 0x090 // [1]68 U Maximum Threshold
#define VP_091_U_MIN 0x091 // [1]68 U Minimum Threshold
#define VP_092_V_MAX 0x092 // [1]68 V Maximum Threshold
#define VP_093_V_MIN 0x093 // [1]68 V Minimum Threshold
// [1]71 $7.32.1 Adjust-Curve
#define VP_094_RANGE1 0x094 // [1]72 Range 1 End Position
#define VP_095_RANGE2 0x095 // [1]72 Range 2 End Position
#define VP_096_RANGE3 0x096 // [1]72 Range 3 End Position
#define VP_097_RANGE4 0x097 // [1]72 Range 4 End Position
#define VP_098_RANGE5 0x098 // [1]72 Range 5 End Position
#define VP_099_RANGE6 0x099 // [1]72 Range 6 End Position
#define VP_094_099_RANGE 0x094 // [1]72 Range
#define VP_09A_SLOPE1 0x09A // [1]72 Range 1 Slope
#define VP_09B_SLOPE2 0x09B // [1]72 Range 2 Slope
#define VP_09C_SLOPE3 0x09C // [1]72 Range 3 Slope
#define VP_09D_SLOPE4 0x09D // [1]72 Range 4 Slope
#define VP_09E_SLOPE5 0x09E // [1]72 Range 5 Slope
#define VP_09F_SLOPE6 0x09F // [1]72 Range 6 Slope
#define VP_0A0_SLOPE7 0x0A0 // [1]72 Range 7 Slope
#define VP_09A_0A0_SLOPE 0x09A // [1]72 Range Slope
#define VP_0A1_DI_OFFSET 0x0A1 // [1]72 RGB output data offset
// [1]73 $7.32.2 LUT Correction
#define VP_0A2_GAMMA_ATTR 0x0A2
#define VP_MASK_GAMMA_LUT_EN 0x01 // [1]73 Gamma LUT Enable
#define VP_MASK_GAMMA_CURVE_EN 0x02 // [1]72 Gamma Curve Enable
#define VP_MASK_GAMMA_LUT_MODE 0x04 // [1]73 Gamma LUT RAM Mapping Mode
// [1]76 $7.35 PLL and OSC Pads
#define VP_0A4_PLL_VND 0x0A4 // [1]76 PLL N Value
#define VP_0A50A6_PLL_VMD 0x0A5 // [1]76 PLL M Value
#define VP_0A6_PLL_ATTR1 0x0A6 // [1]76
#define VP_MASK_PLL_VMD_MSB 0x07 // [1]76
#define VP_MASK_PLL_VMTDIV 0x08 // [1]76 Output clock test enable
#define VP_MASK_PLL_VPD 0x70 // [1]76 PLL D Value
#define VP_MASK_PLL_HALFCK 0x80 // [1]76 Half clock output
#define VP_0A7_PLL_ATTR2 0x0A7 // [1]76
#define VP_MASK_PLL_LEN 0x01 // [1]76 Lock enable
#define VP_MASK_PLL_VPRST 0x02 // [1]76 VCO Reset
#define VP_MASK_PLL_VPLPFS 0x04 // [1]76 PLL Lpf select
#define VP_MASK_PLL_VFSEL 0x08 // [1]76 VCO frequency range select
#define VP_MASK_PLL_R 0x30 // [1]76 REF skew control
#define VP_MASK_PLL_S 0xC0 // [1]76 SEL skew control
// [1]77 $7.36 TIMER
#define VP_0BA_TIMER0_COUNT 0x0BA // [1]77 Timer0 Count value
#define VP_0BB_TIMER0_ATTR 0x0BB // [1]77 Timer0 Attribute
#define VP_MASK_TIMER0_BASE_MODE 0x03 // [1]77 Timer0 Count Base
#define VP_MASK_TIMER0_EN 0x04 // [1]77 Timer0 Enable
#define VP_MASK_TIMER0_MODE 0x08 // [1]77 Timer0 Count Mode
#define VP_0BC_TIMER1_COUNT 0x0BC // [1]77 Timer1 Count value
#define VP_0BD_TIMER1_ATTR 0x0BD // [1]77 Timer1 Attribute
#define VP_MASK_TIMER1_BASE_MODE 0x03 // [1]77 Timer1 Count Base
#define VP_MASK_TIMER1_EN 0x04 // [1]77 Timer1 Enable
#define VP_MASK_TIMER1_MODE 0x08 // [1]77 Timer1 Count Mode
// [1]79 $7.37 GPI and KEY Function
#define VP_0C0_DB 0x0C0 // [1]79
#define VP_MASK_KEY_SEL 0x07 // [1]79 Input pinsselect
#define VP_MASK_KEY_DB 0x18 // [1]79 GPI debounce setup
#define VP_MASK_POWER_DB 0xE0 // [1]89 Feedback debounce setup
#define VP_0C1_KEY_ACK 0x0C1 // [1]79 GPI read back status
#define VP_0C2_KEY_STATUS 0x0C2 // [1]79 Real time GPI status
#define VP_0C3_KEY_POL 0x0C3 // [1]79 GPI Polarity
#define VP_0C4_KEY_TYPE_1234 0x0C4 // [1]79 GPI[4:1] Type setup
#define VP_MASK_KEY_TYPE_1 0x03
#define VP_MASK_KEY_TYPE_2 0x0C
#define VP_MASK_KEY_TYPE_3 0x30
#define VP_MASK_KEY_TYPE_4 0xC0
#define VP_0C5_KEY_TYPE_5678 0x0C5 // [1]79 GPI[8:5] Type setup
#define VP_MASK_KEY_TYPE_5 0x03
#define VP_MASK_KEY_TYPE_6 0x0C
#define VP_MASK_KEY_TYPE_7 0x30
#define VP_MASK_KEY_TYPE_8 0xC0
// [1]38 $7.16 External Pin Setup
#define VP_0C8_EXT_ATTR1 0x0C8 // [1]38 EXT Attribute 1
#define VP_MASK_STH_M0 0x01 // STH Output Selection
#define VP_MASK_STV_M0 0x02 // STV Output Selection
#define VP_MASK_RL_M0 0x04 // TCON R/L
#define VP_MASK_UD_M0 0x08 // TCON U/D
#define VP_MASK_Q2H_M0 0x10 // Q2H Output Polarity
#define VP_MASK_STH_M1 0x20 // STH Output Selection
#define VP_MASK_STV_M1 0x40 // STV Output Selection
#define VP_MASK_RL_M1 0x80 // TCON R/L
#define VP_0C9_EXT_ATTR2 0x0C9 // [1]38 EXT Attribute 2
#define VP_MASK_UD_M1 0x01 // TCON U/D
#define VP_MASK_Q2H_M1 0x02 // Q2H Output Polarity
#define VP_MASK_STH_M3 0x04 // STH Output Selection
#define VP_MASK_STV_M3 0x08 // STV Output Selection
#define VP_MASK_RL_M3 0x10 // TCON R/L
#define VP_MASK_UD_M3 0x20 // TCON U/D
#define VP_MASK_Q2H_M3 0x40 // Q2H Output Polarity
#define VP_MASK_EXTPIN 0x80 //
// [1]81 $7.38 Auto Detection
#define VP_0CB_MODECHG_MRG 0x0CB // Auto Detection VS Threshold
#define VP_MASK_MODECHG_MRG 0x0F // [1]81 VS maxium threshold
#define VP_MASK_MCU_DEBUG 0x80 // ???
// [1]82 $7.39 EEPROM Setup
// [1]83 $7.40 Serial Peripheral Interface (SPI)
#define VP_0CC_SPI_ATTR 0x0CC
#define VP_MASK_SERIAL_CKEN_SEL 0x07 // [1]82 EEPROM Read/Write Speed
#define VP_MASK_SPI_EN 0x08 // [1]83 SPI Enable
#define VP_MASK_SPI_SPEED 0x30 // [1]83 SPI Speed Select
#define VP_MASK_SPI_MODE 0xC0 // [1]83 SPI Mode Select
#define VP_0CD_I2C_SLAVE 0x0CD // [1]82 Script Control I2C Command Slave Setup
// [1]84 $7.41 Power Sequence Control
#define VP_0CF0D5_P1_HSYNC 0x0CF // [1]84 Phase 1 Delay with HS
#define VP_0D00D5_P2_HSYNC 0x0D0 // [1]84 Phase 2 Delay with HS
#define VP_0D10D5_P3_HSYNC 0x0D1 // [1]84 Phase 3 Delay with HS
#define VP_0D20D5_P4_HSYNC 0x0D2 // [1]84 Phase 4 Delay with HS
#define VP_0D30D5_P5_HSYNC 0x0D3 // [1]84 Phase 5 Delay with HS
#define VP_0D40D5_P6_HSYNC 0x0D4 // [1]84 Phase 6 Delay with HS
#define VP_0D5_POWER_HSYNC 0x0D5 // [1]84 Phase Delay with HS
#define VP_MASK_P1_HSYNC_MSB 0x01
#define VP_MASK_P2_HSYNC_MSB 0x02
#define VP_MASK_P3_HSYNC_MSB 0x04
#define VP_MASK_P4_HSYNC_MSB 0x08
#define VP_MASK_P5_HSYNC_MSB 0x10
#define VP_MASK_P6_HSYNC_MSB 0x20
#define VP_MASK_DATA_CTRL 0x40 // [1]84 Data Output Control enable
#define VP_MASK_POWER_EN 0x80 // [1]84 Power Sequence Function enable
#define VP_0D6_P12_VSYNC 0x0D6 // [1]84 Phase 1 & 2 Delay with VS
#define VP_MASK_P1_VSYNC 0x0F
#define VP_MASK_P2_VSYNC 0xF0
#define VP_0D7_P34_VSYNC 0x0D7 // [1]84 Phase 3 & 4 Delay with VS
#define VP_MASK_P3_VSYNC 0x0F
#define VP_MASK_P4_VSYNC 0xF0
#define VP_0D8_P56_VSYNC 0x0D8 // [1]84 Phase 5 & 6 Delay with VS
#define VP_MASK_P5_VSYNC 0x0F
#define VP_MASK_P6_VSYNC 0xF0
#define VP_0D9_POWER_ATTR 0x0D9 // [1]84 Phase Polarity
#define VP_MASK_P1_POL 0x01
#define VP_MASK_P2_POL 0x02
#define VP_MASK_P3_POL 0x04
#define VP_MASK_P4_POL 0x08
#define VP_MASK_DATA_UP 0x70 // [1]84 Data Control Phase select
#define VP_0DA_POWER_SEL 0x0DA // [1]84 Power Sequence output control
#define VP_0DB_P56_ATTR 0x0DB // [1]84 Power phase 5 & 6 output select
#define VP_MASK_P5 0x07 // [1]84
#define VP_MASK_P5_POL 0x08
#define VP_MASK_P6 0x70 // [1]85
#define VP_MASK_P6_POL 0x80
// [1]86 $7.42 PWM Function
// [1]86 PWM1 Function
#define VP_0DE0E1_SYNC_DELAY 0x0DE // [1]86 Synchronize delay time
#define VP_0DF0E1_PWM1_REF 0x0DF // [1]86 PWM1/PWM3 Reference Frequency[7:0]
#define VP_0E00E1_PWM1_FREQ 0x0E0 // [1]86 PWM1 Frequency[7:0]
#define VP_0E1_PWM1_ATTR 0x0E1 // [1]86 PWM1 Attribute
#define VP_MASK_PWM1_REF_MSB 0x03 // [1]86 PWM1/PWM3 Reference Frequency[9:8]
#define VP_MASK_PWM1_FREQ_MSB 0x10 // [1]86 PWM1 Frequency[8]
#define VP_MASK_SYNC_DELAY_MSB 0x40 // [1]86
#define VP_0E20E3_PWM1_DUTY 0x0E2 // [1]86 PWM1 Duty[8:0]
#define VP_0E3_PWM1_DUTY_MSB 0x0E3 // [1]86
// [1]86 PWM2 Function
#define VP_0E40E7_PWM2_REF 0x0E4 // [1]86 PWM2 Reference Frequency[7:0]
#define VP_0E50E7_PWM2_FREQ 0x0E5 // [1]86 PWM2 Frequency[7:0]
#define VP_0E6_PWM_SYNC_DELAY 0x0E6 // [1]86 PWM2 delay phase to PWM1
#define VP_0E7_PWM2_ATTR 0x0E7 // [1]86 PWM2 Attribute
#define VP_MASK_PWM2_REF_MSB 0x03 // [1]86 PWM2 Reference Frequency
#define VP_MASK_PWM2_FREQ_MSB 0x10 // [1]86 PWM2 Frequency
#define VP_MASK_PWM_SYNC_DELAY_MSB 0x20 // [1]86 PWM2
#define VP_0E80E9_PWM2_DUTY 0x0E8 // [1]86 PWM2 Duty[8:0]
#define VP_0EA_PWM12_ATTR 0x0EA // [1]86 PWM12 Attribute
#define VP_MASK_PWM1_SYNC 0x01 // [1]86 PWM1 Synchronized wiht VSYNC
#define VP_MASK_PWM1_POL 0x02 // [1]86 PWM1 Output Polarity
#define VP_MASK_PWM1_SEL 0x04 // [1]86 PWM1 Output select
#define VP_MASK_SYNC_OHS 0x08 // [1]86 PWM1 Output select
#define VP_MASK_PWM2_SYNC 0x10 // [1]86 PWM2 Synchronized wiht VSYNC
#define VP_MASK_PWM2_POL 0x20 // [1]86 PWM2 Output Polarity
#define VP_MASK_PWM2_SYNC_EN 0x40 // [1]86 PWM2 PWM2 synchronized with PWM1
#define VP_MASK_PWM2_SEL 0x80 // [1]87 PWM2 Output select
// [1]88 $7.43 Feedback PWM Control
// [1]88 PWM3 Function
#define VP_0EB_PWM3_FREQ 0x0EB // [1]88 PWM3 Frequency[7:0]
#define VP_0EC_PWM3_DUTY 0x0EC // [1]88 PWM3 Duty[7:0]
// [1]76 PWM4 Function
#define VP_0ED_PWM4_FREQ 0x0ED // [1]88 PWM4 Frequency[7:0]
#define VP_0EE_PWM4_DUTY 0x0EE // [1]88 PWM4 Duty[7:0]
#define VP_0EF_FB_LOW 0x0EF // [1]88 Feedback tracer low limit
#define VP_0F0_FB_HIGH 0x0F0 // [1]88 Feedback tracer high limit
#define VP_0F1_PWM34_ATTR 0x0F1 // [1]88 PWM34 Attribute
#define VP_MASK_PWM3_POL 0x01 // [1]88 PWM3 Output Polarity
#define VP_MASK_PWM3_FB 0x02 // [1]88 PWM3 Feedback Enable
#define VP_MASK_PWM3_SEL 0x04 // [1]88 PWM3 Synchronization Source
#define VP_MASK_PWM3_SYNC 0x08 // [1]88 PWM3 Mode
#define VP_MASK_PWM4_POL 0x10 // [1]88 PWM4 Output Polarity
#define VP_MASK_PWM4_FB 0x20 // [1]88 PWM4 Feedback Enable
#define VP_MASK_PWM4_SEL 0x40 // [1]88 PWM4 Synchronization Source
#define VP_MASK_PWM4_SYNC 0x80 // [1]88 PWM4 Mode
// [1]90 $7.44 IR Decoder Function
#define VP_0F5_IR_DATA_BAR 0x0F5 // [1]90 IR /Data
#define VP_0F6_IR_CODE_BAR 0x0F6 // [1]90 IR /Code
#define VP_0F7_IR_DATA 0x0F7 // [1]90 IR Data
#define VP_0F8_IR_CODE 0x0F8 // [1]90 IR Code
#define VP_0F9_IR_UDCC_BAR 0x0F9 // [1]90 User Defined Customer /Code
#define VP_0FA_IR_UDCC 0x0FA // [1]90 User Defined Customer Code
#define VP_0F90FA_IR_UDCC 0x0F9 // [1]90 User Defined Customer Code
#define VP_0FB_IR_ATTR 0x0FB // [1]90 IR Attribute
#define VP_MASK_IR_EN 0x01 // [1]90 IR Decoder Enable 0=Normal, 1=Invert
#define VP_MASK_IR_POL 0x02 // [1]90 IR Polarity 0=Normal, 1=Invert
#define VP_MASK_IR_BASE 0x1C // [1]90 IR Clock Base
#define VP_MASK_IR_CHECK 0xE0 // [1]90 IR Check Items
#define VP_0FC_IR_ATTR2 0x0FC // IR Attribute 2
#define VP_MASK_IR_DISREPT 0x01 // [1]90 Repeat code detection enable
#define VP_MASK_IR_DB 0x06 // [1]91 IR debounce setup
#define VP_MASK_IR_TYPE 0x10 // [1]91 IR Code Type
#define VP_101_AFE_ATTR 0x101
#define VP_MASK_GPO_STATUS 0x04 // [1]20 GPO Output source select
#define VP_MASK_VD_PATH 0x10 // [1]45 Data path select
#define VP_MASK_VD_SYNC 0x20 // [1]50 Video Decoder Sync select
#define VP_MASK_VD_CLK1 0x40 // [1]27 Video Decoder Path Clock Source Select
#define VP_MASK_VD_CLK2 0x80 // [1]27 Video Decoder Path Clock Source Select
// [1]94 $7.45.2 Analog Input Path
#define VP_102_DVP_ATTR 0x102
#define VP_MASK_ANC_SEL 0x01 // [1]94 Chroma Path Select
#define VP_MASK_ANY_SEL 0x02 // [1]94 Luma Path Select
#define VP_MASK_ADC1_EN 0x04 // [1]94 ADC 1 Enable
#define VP_MASK_SEL1 0x08 // [1]94 Analog MUX Select for ADC1
#define VP_MASK_GAIN1_SEL 0x10 // ???
#define VP_MASK_ADC2_EN 0x20 // [1]94 ADC 2 Enable
#define VP_MASK_SEL2 0x40 // [1]94 Analog MUX Select for ADC2
#define VP_MASK_GAIN2_SEL 0x80 // ???
// [1]97 $7.45.4 Luminance Process
#define VP_103_LUMA_PATH3 0x103
#define VP_MASK_CHT_EN 0x01 // [1]97 Chroma Trap Enable
#define VP_MASK_CHT_SEL 0x02 // [1]97 Chroma-Trap Control (Internal Test)
#define VP_MASK_PREF_EN 0x04 // [1]97 Luma Pre-Filter Enable (Y/C=OFF, CVBS=ON)
#define VP_MASK_YC_EN 0x08 // [1]95 Y/C Mode Enable
#define VP_MASK_VD_MON 0x80 // [1]20 Video Decoder status output select
// [1]96 $7.45.3 Color Standard Setting and detect
#define VP_104_VD_MODE 0x104 // [1]
#define VP_MASK_STD_SEL1 0x07 // [1]96 Color Standard Setup for Manual Setting and Semi-Auto on 50Hz
#define VP_MASK_STD_AUTO 0x08 // [1]96 Color Standard Detect
#define VP_MASK_FSEL 0x10 // [1]96 Manual 50/60Hz select
#define VP_MASK_AUFD 0x20 // [1]96 Auto 50/60Hz detect
#define VP_105_LUMA_ATTR 0x105 // [1]97
#define VP_MASK_BPASS_SEL 0x07 // [1]97 Band Pass Frequency Select
#define VP_MASK_COR_SEL 0x18 // [1]97 Coring circuit amplitude value
#define VP_MASK_APER_SEL 0x60 // [1]97 Aperture factor
#define VP_106_DVP_BRIGHTNESS 0x106 // [1]98 Brightness
#define VP_107_DVP_CONTRAST 0x107 // [1]98 Contrast
#define VP_108_DVP_BLACKLEVEL 0x108 // [1]98 Blacklevel
// [1]99 $7.45.5 Chroma Process
#define VP_109_DVP_SATURATION 0x109 // [1]99 Saturation Value
#define VP_10A_DVP_HUE 0x10A // [1]99 Chrominance HUE control
#define VP_10B_UGAIN 0x10B // [1]99 U Gain Value Adjustment
#define VP_10C_VGAIN 0x10C // [1]99 V Gain Value Adjustment
#define VP_10D_YDEL 0x10D // [1]98
#define VP_MASK_YDEL 0x0F // [1]98 Y Data Path Delay
#define VP_MASK_STD_SEL2 0x70 // [1]96 Color Standard Setup for Semi-Auto on 60Hz
#define VP_MASK_STD_MODE 0x80 // [1]96 Auto Color Standard Detect Mode Select
#define VP_10E_CHROMA_GAIN 0x10E // [1]99 Chroma Gain
#define VP_MASK_CHROMA_GAIN 0x7E
#define VP_MASK_CHROMA_GAIN_SEL 0x80
#define VP_10F110_GAIN_CTRL 0x10F // [1]99 Chroma Gain Reference value
#define VP_110_CHROMA_ATTR1 0x110 // [1]99
#define VP_MASK_GAIN_CTRL_MSB 0x01 // [1]99
#define VP_MASK_AUTO_KILL 0x02 // [1]99 Auto color kill from color detect
#define VP_MASK_CDV_SEL 0x04 // [1]99 TV / VCR Mode Select
#define VP_MASK_CCIR_EN 0x08 // [1]100 CCIR Mode
#define VP_MASK_GAIN_CTRL_SPEED 0x30 // [1]100 Auto Chroma Gain Loop Filter
#define VP_MASK_SECAM_INVERT 0x40 // [1]100 SECAM Invert Enable
#define VP_MASK_SXCR 0x80 // [1]100 SECAM Cross Color Reduction
#define VP_111_THRESHOLD_SECAM 0x111 // [1]100 Color Killer Threshold for SECAM
#define VP_112_THRESHOLD_QAM 0x112 // [1]100 Color Killer Threshold for PAL and NTSC
#define VP_113_SECAM_SENSITIVE 0x113 // [1]100 SECAM switch sensitive level
#define VP_114_PAL_SENSITIVE 0x114 // [1]100 PAL switch sensitive level
#define VP_115_CHROMA_BOUND 0x115 // [1]100
#define VP_MASK_LOWER_BOUND 0x0F // [1]100 Color Standard Detect Threshold 1
#define VP_MASK_UPPER_BOUND 0xF0 // [1]100 Color Standard Detect Threshold 2
#define VP_116_CHROMA_ATTR2 0x116
#define VP_MASK_CHROMA_LPPI1 0x03 // [1]100 Chroma Low Pass Filter Factor 1
#define VP_MASK_CHROMA_LPPI2 0x0C // [1]100 Chroma Low Pass Filter Factor 2
#define VP_MASK_SECS_SEL 0x10 // [1]100 SECAM freq. synchronize
#define VP_MASK_SQP_LPPI 0x60 // [1]100 Sub-Carrier Phase Detect factor 1
#define VP_MASK_SQP_SPUP 0x80 // [1]100 Sub-Carrier Phase Detect factor 2
#define VP_117_CHROMA_ATTR3 0x117 // [1]100
#define VP_MASK_STD_COUNT 0x3F // [1]96 Color Standard Detect Ready Threshold
#define VP_MASK_CHROMA_PHASE 0x40 // [1]100 Chroma Phase Detect Mode
#define VP_MASK_COMPENSATER_SEL 0x80 // [1]100 Sub-Carrier Lock Type
// [1]101 $7.45.6 Synchronization Process
#define VP_118_SYNC_IDEL 0x118 // [1]101 Horizontal increment delay
#define VP_119_SYNC_HSYS 0x119 // [1]101 Horizontal Sync Start
#define VP_11A_SYNC_HSYE 0x11A // [1]101 Horizontal Sync End
#define VP_11B_SYNC_HCS 0x11B // [1]101 Clamp Signal Start
#define VP_11C_SYNC_HCE 0x11C // [1]101 Clamp Signal End
#define VP_11D_SYNC_HSS 0x11D // [1]101 Horizontal Delay
#define VP_11E_BGPU_POINT 0x11E // [1]101 Burst Gap Start Point
#define VP_11F121_AGC_MASK_S 0x11F // [1]101 AGC Mask Start Point
#define VP_120121_AGC_MASK_E 0x120 // [1]101 AGC Mask End Point
#define VP_121_AGC_MASK 0x121 // [1]101 AGC Mask
#define VP_MASK_AGC_E_MSB 0x03
#define VP_MASK_AGC_S_MSB 0x30
#define VP_122_HLCK_THD 0x122 // [1]101 H-Lock Detect Threshold
#define VP_123_SLICER_THD 0x123 // [1]101 Sync-Slicer Threshold
#define VP_124_SYNC_ATTR1 0x124
#define VP_MASK_VNOISE_MODE 0x03 // [1]101 Vsync Detection Mode
#define VP_MASK_FIDT_THD 0xF0 // [1]101 50/60Hz Detect Threshold
#define VP_125_SYNC_ATTR2 0x125 // [1]101
#define VP_MASK_SYNC_LPADJ 0x03 // [1]101 Low Pass Filter Margin Value
#define VP_MASK_SYNC_PDGAIN 0x0C // [1]101 Phase Detection Margin Value
#define VP_MASK_SYNC_LPLMT 0x10 // [1]101 Low pass filter trace value
#define VP_MASK_SYNC_HPLL 0x20 // [1]101 HPLL Mode Enable
#define VP_MASK_VTRC 0x80 // [1]101 VCR Mode Enable
// [1]104 $7.45.8 Analog AGC Control
#define VP_126128_GAIN1_VALUE 0x126
#define VP_127128_GAIN2_VALUE 0x127
#define VP_128_GAIN_ATTR 0x128
#define VP_MASK_GAIN1_VALUE_MSB 0x01 // [1]104 Fixed Gain Value for ADC1
#define VP_MASK_FIXGAIN1_EN 0x02 // [1]104 Auto Gain Control Enable fro ADC1
#define VP_MASK_GAIN2_VALUE_MSB 0x10 // [1]104 Fixed Gain Value for ADC2
#define VP_MASK_FIXGAIN2_EN 0x20 // [1]104 Auto Gain Control Enable fro ADC2
#define VP_MASK_GAIN_HOLD 0x80 // [1]104 Auto Gain Control Hold
// [1]105 $7.45.9 Analog Clamp Control
#define VP_129_AAGC_ATTR 0x129
#define VP_MASK_GAIN_SEL 0x01 // [1]104 Gain Source Select
#define VP_MASK_GAIN_HLCK 0x02 // [1]104 Fixed Gain Enable on HLCK
#define VP_MASK_AAGC_VSMODE 0x04 // [1]105 Analog Clamp and Gain Vsync Mode
#define VP_MASK_MACROVISION_EN 0x08 // [1]105 Analog Clamp and GAIN Disable on VSYNC
#define VP_MASK_GAIN_THB 0xF0 // [1]104 AGC Bottom Threshold Value
#define VP_12A_ACLAMP_LEVEL 0x12A // [1]105 Analog Clamp Level
#define VP_12B_ACLAMP_ATTR 0x12B // [1]105
#define VP_MASK_ACLAMP1_EN 0x01
#define VP_MASK_ACLAMP1_MODE 0x02
#define VP_MASK_ACLAMP1_SPEED 0x0C
#define VP_MASK_ACLAMP2_EN 0x10
#define VP_MASK_ACLAMP2_MODE 0x20
#define VP_MASK_ACLAMP2_SPEED 0xC0
// [1]106 $7.45.10 Digital AGC and Clamp Control
#define VP_12C12E_DGAIN1_VALUE 0x12C // [1]106
#define VP_12D12E_DGAIN2_VALUE 0x12D // [1]106
#define VP_12E_DAGC_ATTR 0x12E // [1]106
#define VP_MASK_DGAIN1_VALUE_MSB 0x01
#define VP_MASK_FIXDGAIN1_EN 0x02 // [1]106 Digital Fixed Gain Control Enable for ADC1
#define VP_MASK_DGAIN1_SEL 0x04 // [1]106 Gain source select for ADC1
#define VP_MASK_DGAIN1_AUTO 0x08 // [1]106 Digital AGC1 and Clamp Auto Enable
#define VP_MASK_DGAIN2_VALUE_MSB 0x10
#define VP_MASK_FIXDGAIN2_EN 0x20 // [1]106 Digital Fixed Gain Control Enable for ADC2
#define VP_MASK_DGAIN2_SEL 0x40 // [1]106 Gain source select for ADC2
#define VP_MASK_DGAIN2_AUTO 0x80 // [1]107 Digital AGC2 and Clamp Auto Enable
#define VP_12F_DCLAMP_ATTR1 0x12F // [1]106
#define VP_MASK_DCLAMP1_EN 0x01
#define VP_MASK_DCLAMP1_HOLD 0x02
#define VP_MASK_DCLAMP1_TYPE 0x04 // [1]106 Clamp Level for ADC1 Channel
#define VP_MASK_DCLAMP1_MODE 0x08 // [1]105 Clamp 1 Type
#define VP_MASK_DCLAMP2_EN 0x10 // [1]107
#define VP_MASK_DCLAMP2_HOLD 0x20
#define VP_MASK_DCLAMP2_TYPE 0x40 // [1]107 Clamp Level for ADC2 Channel
#define VP_MASK_DCLAMP2_MODE 0x80 // [1]105 Clamp 2 Type
#define VP_130_DCLAMP_ATTR2 0x130
#define VP_MASK_CLAMP_SPEED 0x0F // [1]107 Digital Clamp Speed
#define VP_MASK_DAGC_VSMODE 0x10 // [1]107 Digital AGC VSYNC Mode
#define VP_MASK_HCLK_SEL 0xC0 // [1]13 Video Decoder Lock source for interrupt select
#define VP_131_DCLAMP_VALUE 0x131 // [1]107
// [1]110 $7.45.13 Comb Filter Control
#define VP_132_COMB_NRTH 0x132 // [1]110 Noise Reduce Threshold for 2D Comb Filter
#define VP_133_COMB_THD 0x133 // [1]110 Threshold for Filter Selection
#define VP_134_COMB_ATTR 0x134 // [1]110 COMB Attribute
#define VP_MASK_COMB_THD_MSB 0x0F // Threshold for Filter Selection
#define VP_MASK_COMB_YDEL 0x10 // Y Data Path Delay
#define VP_MASK_COMB_SEL 0x20 // Comb Filter Select
#define VP_MASK_FREQ_SEL 0x40 // Frequency Select
#define VP_MASK_COMB_EN 0x80 // Adaptive Comb Filter Enable
#define VP_135_HS_DLY 0x135 // [1]110 COMB Attribute
#define VP_MASK_HS_DELAY 0x07 // [1]110 HSYNC Delay
#define VP_MASK_HS_MASK_EN 0x10 // [1]110 HSYNC Mask Enable
#define VP_MASK_VS_MASK_EN 0x20 // [1]110 VSYNC Mask Enable
#define VP_MASK_SQP_LMT 0x40 // [1]100 Sub-Carrier Phase Detect factor 3
// [1]108 $7.45.11 ADC Control
#define VP_136_AFE_CTRL 0x136
#define VP_MASK_SAD10 0x01 // ADC1 Switch 1 Enable
#define VP_MASK_SAD11 0x02 // ADC1 Switch 2 Enable
#define VP_MASK_AMUX1 0x04 // Bypass PGA
#define VP_MASK_SAD20 0x10 // ADC2 Switch 1 Enable
#define VP_MASK_SAD21 0x20 // ADC2 Switch 2 Enable
#define VP_MASK_AMUX2 0x40 // Bypass PGA
#define VP_MASK_ADCTEST 0x80 // ADC Test Mode Enable
// [1]109 $7.45.12 AFE PLL Clock Control
#define VP_137_AFE_PLL 0x137
#define VP_MASK_INV_CLK 0x01 // [1]109 Clock Polarity
#define VP_MASK_DVT_PLL 0x02 // [1]109 Source Select
#define VP_MASK_ADCCLK_INV 0x04 // [1]108 ADC Clock Polarity
#define VP_MASK_ADCCLK_SEL 0x08 // [1]108 CLK Source Select
#define VP_MASK_RMUX 0x10 // [1]109 Reference Clock Select
#define VP_MASK_PMUX 0x20 // [1]109 PLL Clock phase shift
#define VP_MASK_CLKMUX 0x40 // [1]109 Internal CLK135 Clock Source Select
#define VP_MASK_EAPLL 0x80 // [1]109 PLL Enable
// [1]115 $7.46.1 OSD Windows Function
// [1]115 OSD Windows 1 Function
#define VP_13813A_OSD1_H_POSITION 0x138 // [1]115 OSD1 Start X position
#define VP_13913A_OSD1_V_POSITION 0x139 // [1]115 OSD1 Start Y position
#define VP_13A_OSD1_POSITION_MSB 0x13A // [1]115
#define VP_MASK_V_POSITION_MSB 0x01 // [JC010] OSD Image Retention issue fixed by JC 09:15AM 2006/04/25
#define VP_MASK_H_POSITION_MSB 0x30 // [JC010] OSD Image Retention issue fixed by JC 09:15AM 2006/04/25
#define VP_MASK_H_POSITION_MSB9 0x20 // [JC010] OSD Image Retention issue fixed by JC 09:15AM 2006/04/25
#define VP_MASK_H_POSITION_MSB8 0x10 // [JC010] OSD Image Retention issue fixed by JC 09:15AM 2006/04/25
#define VP_13B_OSD1_WIDTH 0x13B // [1]115 OSD1 Width
#define VP_13C_OSD1_HEIGHT 0x13C // [1]115 OSD1 Height
// [1]118 OSD Windows 1 Attribute
#define VP_13D_OSD1_RAM_INDEX 0x13D // Display RAM Start Index
#define VP_13E_OSD1_FADE_LEVEL 0x13E // OSD Fade Level
#define VP_MASK_OSD1_FADE 0x0F
#define VP_MASK_OSD1_WHMIRROR_EN 0x10 // Window Horizontal Mirror
#define VP_MASK_OSD1_WVMIRROR_EN 0x20 // Window Vertical Mirror
#define VP_MASK_OSD1_FHMIRROR_EN 0x40 // Character Horizontal Mirror
#define VP_MASK_OSD1_FVMIRROR_EN 0x80 // Character Vertical Mirror
#define VP_13F_OSD1_BORDER_SEL 0x13F
#define VP_140_OSD1_ATTR1 0x140
#define VP_MASK_OSD1_BORDER_HW 0x03
#define VP_MASK_OSD1_BORDER_VW 0x0C
#define VP_MASK_OSD1_BORDER_COLOR 0x70
#define VP_141_OSD1_ATTR2 0x141
#define VP_MASK_OSD1_CHAR_SIZE_H 0x07 // Horizontal Character Size
#define VP_MASK_OSD1_CHAR_SIZE_V 0x70 // Vertical Character Size
#define VP_142_OSD1_ATTR3 0x142
#define VP_MASK_OSD1_LNNUM 0x0F // OSD1 vanish Line Number
#define VP_MASK_OSD1_LNDIR 0x10 // OSD1 vanish Line Direction
#define VP_143_OSD1_ATTR4 0x143
#define VP_MASK_OSD1_EN 0x01 // [1]143 OSD Window Enable
#define VP_MASK_OSD1_BLINKPERIOD 0x0E // [1]142 OSD Blink Period (in VSYNC)
#define VP_MASK_OSD1_LINE_SPACE 0x70 // [1]142 OSD Line Space
// [1]115 OSD Windows 2 Function
#define VP_146148_OSD2_H_POSITION 0x146 // [1]115 OSD2 Start X position
#define VP_147148_OSD2_V_POSITION 0x147 // [1]115 OSD2 Start Y position
#define VP_148_OSD2_POSITION_MSB 0x148
#define VP_149_OSD2_WIDTH 0x149 // [1]115 OSD2 Width
#define VP_14A_OSD2_HEIGHT 0x14A // [1]115 OSD2 Height
// [1]119 OSD Windows 2 Attribute
#define VP_14B_OSD2_RAM_INDEX 0x14B // Display RAM Start Index
#define VP_14C_OSD2_FADE_LEVEL 0x14C // OSD Fade Level
#define VP_MASK_OSD2_FADE 0x0F
#define VP_MASK_OSD2_WHMIRROR_EN 0x10 // Window Horizontal Mirror
#define VP_MASK_OSD2_WVMIRROR_EN 0x20 // Window Vertical Mirror
#define VP_MASK_OSD2_FHMIRROR_EN 0x40 // Character Horizontal Mirror
#define VP_MASK_OSD2_FVMIRROR_EN 0x80 // Character Vertical Mirror
#define VP_14D_OSD2_BORDER_SEL 0x14D
#define VP_14E_OSD2_ATTR1 0x14E // [1]119
#define VP_MASK_OSD2_BORDER_HW 0x03
#define VP_MASK_OSD2_BORDER_VW 0x0C
#define VP_MASK_OSD2_BORDER_COLOR 0x30
#define VP_14F_OSD2_ATTR2 0x14F // [1]119
#define VP_MASK_OSD2_CHAR_SIZE_H 0x03 // Horizontal Character Size
#define VP_MASK_OSD2_CHAR_SIZE_V 0x0C // Vertical Character Size
#define VP_150_OSD2_ATTR3 0x150
#define VP_MASK_OSD2_LNNUM 0x0F // OSD2 vanish Line Number
#define VP_MASK_OSD2_LNDIR 0x10 // OSD2 vanish Line Direction
#define VP_151_OSD2_ATTR4 0x151 // [1]119
#define VP_MASK_OSD2_EN 0x01 // [1]120 OSD Window Enable
#define VP_MASK_OSD2_BLINKPERIOD 0x0E // [1]119 OSD Blink Period (in VSYNC)
#define VP_MASK_OSD2_LINE_SPACE 0x70 // [1]119 OSD Line Space
// [1]115 OSD Windows 3 Function
#define VP_154156_OSD3_H_POSITION 0x154 // [1]115 OSD3 Start X position
#define VP_155156_OSD3_V_POSITION 0x155 // [1]115 OSD3 Start Y position
#define VP_156_OSD3_POSITION_MSB 0x156
#define VP_157_OSD3_WIDTH 0x157 // [1]115 OSD3 Width
#define VP_158_OSD3_HEIGHT 0x158 // [1]115 OSD3 Height
// [1]120 OSD Windows 3 Attribute
#define VP_159_OSD3_RAM_INDEX 0x159 // [1]120 Display RAM Start Index
#define VP_15A_OSD3_FADE_LEVEL 0x15A // [1]120 OSD Fade Level
#define VP_MASK_OSD3_FADE 0x0F
#define VP_MASK_OSD3_WHMIRROR_EN 0x10 // Window Horizontal Mirror
#define VP_MASK_OSD3_WVMIRROR_EN 0x20 // Window Vertical Mirror
#define VP_MASK_OSD3_FHMIRROR_EN 0x40 // Character Horizontal Mirror
#define VP_MASK_OSD3_FVMIRROR_EN 0x80 // Character Vertical Mirror
#define VP_15B_OSD3_BORDER_SEL 0x15B // [1]120 Font Border Selection
#define VP_15C_OSD3_ATTR1 0x15C // [1]120
#define VP_MASK_OSD3_BORDER_HW 0x03
#define VP_MASK_OSD3_BORDER_VW 0x0C
#define VP_MASK_OSD3_BORDER_COLOR 0x30
#define VP_15D_OSD3_ATTR2 0x15D // [1]120 OSD3 Attribute
#define VP_MASK_OSD3_CHAR_SIZE_H 0x03 // Horizontal Character Size
#define VP_MASK_OSD3_CHAR_SIZE_V 0x0C // Vertical Character Size
#define VP_15E_OSD3_ATTR3 0x15E // [1]121
#define VP_MASK_OSD3_LNNUM 0x0F // OSD3 vanish Line Number
#define VP_MASK_OSD3_LNDIR 0x10 // OSD3 vanish Line Direction
#define VP_15F_OSD3_ATTR4 0x15F // [1]121
#define VP_MASK_OSD3_EN 0x01 // [1]121 OSD Window Enable
#define VP_MASK_OSD3_BLINKPERIOD 0x0E // [1]120 OSD Blink Period (in VSYNC)
#define VP_MASK_OSD3_LINE_SPACE 0x70 // [1]120 OSD Line Space
// [1]122 $7.46.4 External OSD Interface
#define VP_162_EXTOSD_ATTR 0x162 // [1]122 External OSD interface
#define VP_MASK_EXTOSD_EN 0x01 // [1]122 External OSD Enable
#define VP_MASK_EXTBLANK_POL 0x02 // [1]122 External OSD Blank Polarity
#define VP_MASK_OSDHS_POL 0x04 // [1]122 External OSD HS Polarity
#define VP_MASK_OSDVS_POL 0x08 // [1]122 External OSD VS Polarity
#define VP_MASK_OSDCLK_POL 0x10 // [1]122 External OSD CLOCK Polarity
#define VP_MASK_BANK_SEL 0x80 // ???
#define VP_16316E_EXTOSD_COLOR 0x163 // [1]122 External OSD Color
// [1]110
#define VP_170_CSTD_CTRL 0x170 // [1]110
#define VP_MASK_CSTD_PAL60_EN 0x01
#define VP_MASK_SYNC_RDY_EN 0x02
#define VP_MASK_STD_RDY_EN 0x04
#define VP_MASK_SECS_EN 0x08
#define VP_MASK_HLCK_EN 0x10
#define VP_171_CSTD_EN 0x171 // [1]111
#define VP_MASK_CSTD_PAL_EN 0x01
#define VP_MASK_CSTD_PAL_N_EN 0x02
#define VP_MASK_CSTD_SECAM_EN 0x04
#define VP_MASK_CSTD_PAL_M_EN 0x08
#define VP_MASK_CSTD_NTSC443_50_EN 0x10
#define VP_MASK_CSTD_NTSC_M_EN 0x20
#define VP_MASK_CSTD_NTSC443_60_EN 0x40
#define VP_MASK_CSTD_BW_EN 0x80
// [1]112 $7.45.14 Status Register
#define VP_180_DCLAMP1_OUT 0x180
#define VP_181_DCLAMP2_OUT 0x181
#define VP_182185_GAIN_OUT 0x182
#define VP_183185_DGAIN1_OUT 0x183
#define VP_184185_DGAIN2_OUT 0x184
#define VP_185_GAIN_ATTR 0x185
#define VP_MASK_DGAIN1_OUT_MSB 0x01
#define VP_MASK_OVER1 0x02
#define VP_MASK_GAIN_OUT_MSB 0x04
#define VP_MASK_DGAIN2_OUT_MSB 0x10
#define VP_MASK_OVER2 0x20
#define VP_186_DVP_STATUS 0x186 // [1]112
#define VP_MASK_COLOR_STANDARD 0x07 // Color Standard Detection Result
#define VP_MASK_FIDT 0x08 // Vsync Frequency (0=50Hz, 1=60Hz)
#define VP_MASK_HCLK 0x10 // Hsync Lock Status
#define VP_MASK_FFIDT 0x20 // Vsync Frequency (Fast Mode)
#define VP_MASK_SYNC_READY 0x40 // Sync Ready
#define VP_MASK_STD_READY 0x80 // Standard Ready
#define VP_MASK_STATUS (VP_MASK_STD_READY | VP_MASK_SYNC_READY)
#define VP_MASK_STATUS_ (VP_MASK_SYNC_READY | VP_MASK_FFIDT | VP_MASK_HCLK | VP_MASK_FIDT)
#define VP_MASK_STATUS_LOCK (VP_MASK_SYNC_READY | VP_MASK_STD_READY)
#define VP_18718818B_INC_CHRO 0x187 // [1]113 Line-Lock Frequency Output
#define VP_18918B_SUB_FREQ 0x189 // [1]113 Sub-Carrier Frequency Output
#define VP_18A18B_SUB_PHASE 0x18A // [1]113 Sub-Carrier Frequency Phase
#define VP_18B_LLSC_STATUS 0x18B // [1]113
#define VP_MASK_SUB_FREQ_MSB 0x03
#define VP_MASK_COLOR_KILL 0x04 // [1]113 Color kill detect
#define VP_MASK_INC_CHRO_MSB 0x08
#define VP_MASK_SUB_PHASE_MSB 0x70
// [1]81 $7.38 Auto Detection
#define VP_18C_DET_STATUS 0x18C // [1]81
#define VP_MASK_MODE_TYPE 0x01 // [1]81 Mode Status 0=50Hz, 1=60Hz
#define VP_MASK_EVEN_SAME 0x02 // [1]81 EVEN Type status
#define VP_MASK_SYNC_DET 0x04 // [1]81 Sync Status
#define VP_MASK_IEVEN 0x08 // [1]81 EVEN/ODD Information
#define VP_18D_DET_HS_LOW_PULSE 0x18D // [1]81 HS Low pulse in PCLK
#define VP_18E191_DET_HS_TOTAL_WIDTH 0x18E // [1]81 HS Total width in PCLK
#define VP_18F_DET_VS_LOW_PULSE 0x18F // [1]81 VS Low pulse in HS
#define VP_190191_DET_VS_TOTAL_WIDTH 0x190 // [1]81 VS Total width in HS
#define VP_191_DET_TOTAL_WIDTH 0x191 // [1]81 HS in PCLK and VS in HS
#define VP_MASK_VS_TOTAL_WIDTH_MSB 0x03 // Auto Detection VS Total Width MSB
#define VP_MASK_HS_TOTAL_WIDTH_MSB 0x70 // Auto Detection HS Total Width MSB
// [1]59 $7.29 Timing Adjustment
#define VP_192193_COUNT1 0x192 // [1]59 OVREF vs. IVREF Length in OCLK
#define VP_19B_ADC1 0x19B // ???
#define VP_19C_ADC2 0x19C // ???
#define VP_19D_COUNT2 0x19D // [1]59 Line Buffer Error Value in OCLK
// [1]73 $7.32.2 LUT Correction
#define VP_0200_02FF_GAMMA_LUT_R 0x0200 // [1]73 Gamma LUT for R color
#define VP_0300_03FF_GAMMA_LUT_G 0x0300 // [1]73 Gamma LUT for G color
#define VP_0400_04FF_GAMMA_LUT_B 0x0400 // [1]73 Gamma LUT for B color
// [1]116 $7.46.2 OSD Memory Mapping
#define VP_0500_057F_DISPLAY_CODE 0x0500 // Display Character Code
#define VP_0580_05FF_DISPLAY_ATTR 0x0580 // Display Character Attribute
// [1]116 OSD Palette
#define VP_0600_063F_PALETTE 0x0600 // [1]116 Palette (16 x 4 bytes)
// [1]116 User Programmable Font RAM
#define VP_0700_07FF_USER_FONT_RAM 0x0700 // User Font RAM (Bank0 and Bank1)
/* ::::::::::::::::::::::::::::::::::::
Range Definition
:::::::::::::::::::::::::::::::::::: */
#define MAX_DITHERING 2
#define MIN_DITHERING 0
// [1]15
#define MAX_INPUT_H_START 2047
#define MIN_INPUT_H_START 0
#define MAX_INPUT_H_END 2047
#define MIN_INPUT_H_END 0
#define MAX_INPUT_V_START 2047
#define MIN_INPUT_V_START 0
#define MAX_INPUT_V_END 2047
#define MIN_INPUT_V_END 0
// [1]19 Display Window
#define MAX_DISPLAY_H_START 2047 // [1]19 11 bits
#define MIN_DISPLAY_H_START 0
#define MAX_DISPLAY_H_WIDTH 1023 // [1]19 10 bits
#define MIN_DISPLAY_H_WIDTH 0
#define MAX_DISPLAY_V_START 1023 // [1]19 10 bits
#define MIN_DISPLAY_V_START 0
#define MAX_DISPLAY_V_HEIGHT 1023 // [1]19 10 bits
#define MIN_DISPLAY_V_HEIGHT 0
// [1]14 Panel
#define MAX_ACTIVE_H_START 2047 // [1]14 11 bits
#define MIN_ACTIVE_H_START 0
#define MAX_ACTIVE_H_END 2047 // [1]14 11 bits
#define MIN_ACTIVE_H_END 0
#define MAX_ACTIVE_V_START 1023 // [1]14 10 bits
#define MIN_ACTIVE_V_START 0
#define MAX_ACTIVE_V_END 1023 // [1]14 10 bits
#define MIN_ACTIVE_V_END 0
#define MAX_PANEL_HS_WIDTH 2047 // [1]14 11 bits
#define MIN_PANEL_HS_WIDTH 0
#define MAX_PANEL_H_TOTAL 2047 // [1]14 11 bits
#define MIN_PANEL_H_TOTAL 0
#define MAX_PANEL_H_TOTAL_ODD 2047 // [1]14 11 bits
#define MIN_PANEL_H_TOTAL_ODD 0
#define MAX_PANEL_VS_WIDTH 1023 // [1]14 10 bits
#define MIN_PANEL_VS_WIDTH 0
#define MAX_PANEL_V_TOTAL 1023 // [1]14 10 bits
#define MIN_PANEL_V_TOTAL 0
/* ::::::::::::::::::::::::::::::::::::
[1]21,23 Input Channel
:::::::::::::::::::::::::::::::::::: */
#define MAX_INPUT_DATAPATH 255 // [1]21
#define MIN_INPUT_DATAPATH 0
#define MAX_INPUT_MODE 127 // [1]23
#define MIN_INPUT_MODE 0
#define MAX_INPUT_POLARITY 3 // [1]23
#define MIN_INPUT_POLARITY 0
/* ::::::::::::::::::::::::::::::::::::
[1]28 Video Processor
:::::::::::::::::::::::::::::::::::: */
#define MAX_VP_BRIGHTNESS +127 // [1]28 0 = Disable
#define MIN_VP_BRIGHTNESS -127
#define MAX_VP_BRIGHTNESS_OSD 254 // 127 = Disable
#define MIN_VP_BRIGHTNESS_OSD 0
#define MAX_VP_CONTRAST 255 // [1]28 128 = Disable
#define MIN_VP_CONTRAST 0
#define MAX_VP_BLACKLEVEL +127 // [1]28 0 = Disable
#define MIN_VP_BLACKLEVEL -127
#define MAX_VP_BLACKLEVEL_OSD 254 // 127 = Disable
#define MIN_VP_BLACKLEVEL_OSD 0
/* ::::::::::::::::::::::::::::::::::::
[1]30 Zoom HD (Horizontal Zoom Down)
:::::::::::::::::::::::::::::::::::: */
#define MAX_ZOOM_HD_START 2047 // [1]30 11 bits
#define MIN_ZOOM_HD_START 0
#define MAX_ZOOM_HD_SHIFT 1023 // [1]30 10 bits
#define MIN_ZOOM_HD_SHIFT 0
#define MAX_ZOOM_HD_FIX 1023 // [1]30 10 bits
#define MIN_ZOOM_HD_FIX 0
#define MAX_ZOOM_HD_WIDTH 1023 // [1]30 10 bits
#define MIN_ZOOM_HD_WIDTH 0
#define MAX_ZOOM_HD_MODE 15 // [1]30 4 bits
#define MIN_ZOOM_HD_MODE 0
/* ::::::::::::::::::::::::::::::::::::
[1]18 Pattern Color and Type
:::::::::::::::::::::::::::::::::::: */
#define MAX_PATTERN_COLOR_RED 15 // [1]18
#define MIN_PATTERN_COLOR_RED 0
#define MAX_PATTERN_COLOR_GREEN 15 // [1]18
#define MIN_PATTERN_COLOR_GREEN 0
#define MAX_PATTERN_COLOR_BLUE 15 // [1]18
#define MIN_PATTERN_COLOR_BLUE 0
#define MAX_PATTERN_TYPE 3 // [1]18
#define MIN_PATTERN_TYPE 1 // 1=Pure Color, 2=Ramp, 3=Cross
/* ::::::::::::::::::::::::::::::::::::
[1]15 Output Channel
:::::::::::::::::::::::::::::::::::: */
#define MAX_OUTPUT_DATAPATH 255 // [1]15
#define MIN_OUTPUT_DATAPATH 0
#define MAX_OUTPUT_MODE 15 // [1]17
#define MIN_OUTPUT_MODE 0 // [1]17
/* ::::::::::::::::::::::::::::::::::::
VP Interrupt Configuration
:::::::::::::::::::::::::::::::::::: */
#define VP_INT_CFG EXT_INT_NONE
#define VP_USING 2
#if (VP_INT_CFG == EXT_INT0)
#define PIN_VP P3_2 // Ext. INT 0
#define VP_INT 0 /* [2]92 Timer Interrupt Number (Vector=0x03) */
#define VP_INT_TRIGGER IT0 /* [3]64,89 0=Level-activated, 1=Transition-activated */
#define VP_INT_ENABLE EX0 /* [3]64,87 Enable Ext. INT 0 */
#elif (VP_INT_CFG == EXT_INT1)
#define PIN_VP P3_3 // Ext. INT 1
#define VP_INT 2 /* [2]92 Timer Interrupt Number (Vector=0x13) */
#define VP_INT_TRIGGER IT1 /* [2]38 0=Level-activated, 1=Transition-activated */
#define VP_INT_ENABLE EX1 /* [2]39 Enable Ext. INT 1 */
#endif // IR_INT_CFG
/* ::::::::::::::::::::::::::::::::::::
Display Mode
:::::::::::::::::::::::::::::::::::: */
typedef enum DISPLAY_MODE_ENUM
{
DISPLAY_MODE_LINEAR,
DISPLAY_MODE_NONLINEAR,
DISPLAY_MODE_BYPASS,
DISPLAY_MODE_SIZE
} enumDISPLAY_MODE;
/* ::::::::::::::::::::::::::::::::::::
[1]67 Image Filter
:::::::::::::::::::::::::::::::::::: */
typedef enum IMAGE_FILTER_ENUM
{
IMAGE_FILTER_SMOOTH3,
IMAGE_FILTER_SMOOTH2,
IMAGE_FILTER_SMOOTH1,
IMAGE_FILTER_SMOOTH0,
IMAGE_FILTER_NORMAL,
IMAGE_FILTER_SHARP0,
IMAGE_FILTER_SHARP1,
IMAGE_FILTER_SHARP2,
IMAGE_FILTER_SHARP3,
IMAGE_FILTER_SIZE
} enumIMAGE_FILTER;
#define IMAGE_FILTER_MIN IMAGE_FILTER_SMOOTH0
#define IMAGE_FILTER_MAX IMAGE_FILTER_SHARP3
#define IMAGE_FILTER_STEP 1
#define IMAGE_FILTER_OSD_MIN IMAGE_FILTER_SMOOTH0
#define IMAGE_FILTER_OSD_MAX IMAGE_FILTER_SHARP3
#define IMAGE_FILTER_OSD_STEP 1
/* ::::::::::::::::::::::::::::::::::::
TCON Mode
:::::::::::::::::::::::::::::::::::: */
typedef enum TCON_MODE_ENUM
{
TCON_MODE_RU, // Right Up
TCON_MODE_MIN = TCON_MODE_RU,
TCON_MODE_LU, // Left Up
TCON_MODE_LD, // Left Down
TCON_MODE_RD, // Right Down
TCON_MODE_MAX = TCON_MODE_RD,
TCON_MODE_SIZE,
} enumTCON_MODE;
#define VP_DISPLAYMODE OFF
#define VP_SET_BLACKLEVEL ON
#define VP_SET_BRIGHTNESS ON
#define VP_SET_COLORSTANDARD OFF
#define VP_SET_CONTRAST ON
#define VP_SET_IMAGE_FILTER ON
#define VP_SET_IMAGE_MIRROR OFF
#define VP_SET_PLL OFF
#define VP_SET_PWM_DUTY OFF
#define VP_SET_PWM_FREQ OFF
#define VP_SET_PWM_REF OFF
#define VP_SET_TCON_MODE ON
#define VP_SET_TESTPATTERN OFF
/* ------------------------------------
Type Definitions
------------------------------------ */
/* ------------------------------------
Variables Definitions/Declarations
------------------------------------ */
// OP5 OP4 OP3 OP2 Mode
// 0 x x x EEPROM Script Mode
// 1 0 0 0 I2C Mode (0x00..0x0F)
// 1 0 0 1 I2C Mode (0x20..0x2F)
// 1 0 1 0 I2C Mode (0x40..0x4F)
// 1 0 1 1 I2C Mode (0x60..0x6F)
// 1 1 0 0 BiTEKbus Mode (0x81)
// 1 1 0 1 BiTEKbus Mode (0x83)
// 1 1 1 0 BiTEKbus Mode (0x85)
// 1 1 1 1 BiTEKbus Mode (0x87)
sbit VP_nReset = P0 ^ 0;
#define VP_RESET_ON { VP_nReset = LOW; }
#define VP_RESET_OFF { VP_nReset = HIGH; }
#if (VP_IF_CFG == VP_IF_BITEK) // OP5 OP4 OP3 OP2 Mode
#define VP_MAD_IF 0x83 // 1 1 0 1 BiTEKbus Mode (0x83)
#else
#define VP_MAD_IF 0x20 // 1 0 0 1 I2C Mode (0x20..0x2F)
#endif
#define VP_MAD VP_MAD_IF // VP IF MAD
#if (VP_INT_CFG != EXT_INT_NONE)
EXTERN BOOL fVP_IntReady;
#endif // VP_INT_CFG
#ifdef _VP_C_
// VD_N
UB8 CODE abVP_007_0A7_DEFAULT[] = {
// 0 1 2 3 4 5 6 7 8 9 A B C D E F
/* 0 */ 0x00,0x00,0x00,0x00,0x7F,0xFF,0x00,0xAF,0x3B,
/* 1 */ 0x01,0x26,0xA1,0xC1,0xA1,0xA1,0x22,0xC4,0x3B,0x12,0x2E,0x2E,0x22,0xA5,0x6B,0x32,
/* 2 */ 0x02,0x05,0x00,0x06,0x0F,0x88,0x02,0x03,0x04,0x8C,0x66,0x67,0x27,0x51,0x00,0x02,
/* 3 */ 0x37,0x14,0x34,0x00,0x01,0x00,0xC1,0x0A,0x00,0x79,0xF9,0x0C,0x00,0x00,0x3F,0xE0,
/* 4 */ 0x10,0x9F,0xA6,0x50,0x30,0x0D,0x35,0x10,0x99,0x45,0x30,0x0A,0x03,0x10,0x40,0x70,
/* 5 */ 0x2C,0x70,0x01,0x05,0x00,0xEA,0x26,0xA1,0x40,0x45,0x98,0xA9,0x00,0x33,0x00,0x03,
/* 6 */ 0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xB0,0x77,0x00,0x2A,0xA0,0x17,0x09,0x09,
/* 7 */ 0x00,0xC0,0x40,0x00,0xF9,0x00,0x07,0x06,0x06,0x00,0x15,0x05,0x80,0x80,0x80,0x80,
/* 8 */ 0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x40,0x40,0xEF,0x90,0x12,0x87,0x78,0x00,0x00,
/* 9 */ 0xFF,0x00,0xFF,0x00,0x24,0x48,0x6C,0x90,0xB4,0xD8,0x20,0x20,0x20,0x20,0x20,0x20,
/* A */ 0x20,0x00,0x00,0x00,0x88,0x5A,0x22,0x00
};
#else
extern UB8 CODE abVP_007_0A7_DEFAULT[];
#endif /* _VP_C_ */
#ifdef NOT_JUNK
#ifdef _VP_C_
UB8 CODE abGammaR[] = {
0x02,0x05,0x09,0x0D,0x11,0x15,0x19,0x1C,0x1F,0x22,0x24,0x27,0x29,0x2B,0x2E,0x2F,
0x31,0x33,0x35,0x36,0x38,0x39,0x3B,0x3C,0x3D,0x3F,0x40,0x41,0x42,0x43,0x44,0x46,
0x47,0x48,0x49,0x4A,0x4B,0x4B,0x4C,0x4D,0x4E,0x4F,0x50,0x50,0x51,0x52,0x53,0x54,
0x54,0x55,0x56,0x57,0x57,0x58,0x59,0x59,0x5A,0x5B,0x5B,0x5C,0x5D,0x5D,0x5E,0x5F,
0x5F,0x60,0x61,0x62,0x62,0x63,0x63,0x64,0x65,0x65,0x66,0x67,0x67,0x68,0x69,0x69,
0x6A,0x6A,0x6B,0x6C,0x6C,0x6D,0x6D,0x6E,0x6F,0x6F,0x70,0x70,0x71,0x72,0x72,0x73,
0x74,0x74,0x75,0x75,0x76,0x77,0x77,0x78,0x78,0x79,0x7A,0x7A,0x7B,0x7B,0x7C,0x7D,
0x7D,0x7E,0x7E,0x7F,0x80,0x80,0x81,0x81,0x82,0x82,0x83,0x84,0x84,0x85,0x85,0x86,
0x87,0x87,0x88,0x88,0x89,0x8A,0x8A,0x8B,0x8B,0x8C,0x8D,0x8D,0x8E,0x8E,0x8F,0x90,
0x90,0x91,0x91,0x92,0x93,0x93,0x94,0x95,0x95,0x96,0x96,0x97,0x98,0x98,0x99,0x9A,
0x9A,0x9B,0x9C,0x9C,0x9D,0x9E,0x9E,0x9F,0xA0,0xA0,0xA1,0xA1,0xA2,0xA3,0xA4,0xA4,
0xA5,0xA6,0xA6,0xA7,0xA8,0xA8,0xA9,0xAA,0xAB,0xAB,0xAC,0xAD,0xAE,0xAF,0xAF,0xB0,
0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF,
0xC0,0xC1,0xC2,0xC3,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCD,0xCE,0xCF,0xD0,0xD2,
0xD3,0xD4,0xD6,0xD7,0xD8,0xDA,0xDB,0xDC,0xDE,0xDF,0xE1,0xE2,0xE4,0xE5,0xE7,0xE8,
0xEA,0xEB,0xED,0xEE,0xF0,0xF1,0xF3,0xF4,0xF6,0xF8,0xF9,0xFA,0xFC,0xFD,0xFE,0xFF,
};
UB8 CODE abGammaG[] = {
0x02,0x05,0x09,0x0D,0x11,0x15,0x19,0x1C,0x1F,0x22,0x24,0x27,0x29,0x2B,0x2E,0x2F,
0x31,0x33,0x35,0x36,0x38,0x39,0x3B,0x3C,0x3D,0x3F,0x40,0x41,0x42,0x43,0x44,0x46,
0x47,0x48,0x49,0x4A,0x4B,0x4B,0x4C,0x4D,0x4E,0x4F,0x50,0x50,0x51,0x52,0x53,0x54,
0x54,0x55,0x56,0x57,0x57,0x58,0x59,0x59,0x5A,0x5B,0x5B,0x5C,0x5D,0x5D,0x5E,0x5F,
0x5F,0x60,0x61,0x62,0x62,0x63,0x63,0x64,0x65,0x65,0x66,0x67,0x67,0x68,0x69,0x69,
0x6A,0x6A,0x6B,0x6C,0x6C,0x6D,0x6D,0x6E,0x6F,0x6F,0x70,0x70,0x71,0x72,0x72,0x73,
0x74,0x74,0x75,0x75,0x76,0x77,0x77,0x78,0x78,0x79,0x7A,0x7A,0x7B,0x7B,0x7C,0x7D,
0x7D,0x7E,0x7E,0x7F,0x80,0x80,0x81,0x81,0x82,0x82,0x83,0x84,0x84,0x85,0x85,0x86,
0x87,0x87,0x88,0x88,0x89,0x8A,0x8A,0x8B,0x8B,0x8C,0x8D,0x8D,0x8E,0x8E,0x8F,0x90,
0x90,0x91,0x91,0x92,0x93,0x93,0x94,0x95,0x95,0x96,0x96,0x97,0x98,0x98,0x99,0x9A,
0x9A,0x9B,0x9C,0x9C,0x9D,0x9E,0x9E,0x9F,0xA0,0xA0,0xA1,0xA1,0xA2,0xA3,0xA4,0xA4,
0xA5,0xA6,0xA6,0xA7,0xA8,0xA8,0xA9,0xAA,0xAB,0xAB,0xAC,0xAD,0xAE,0xAF,0xAF,0xB0,
0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF,
0xC0,0xC1,0xC2,0xC3,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCD,0xCE,0xCF,0xD0,0xD2,
0xD3,0xD4,0xD6,0xD7,0xD8,0xDA,0xDB,0xDC,0xDE,0xDF,0xE1,0xE2,0xE4,0xE5,0xE7,0xE8,
0xEA,0xEB,0xED,0xEE,0xF0,0xF1,0xF3,0xF4,0xF6,0xF8,0xF9,0xFA,0xFC,0xFD,0xFE,0xFF,
};
UB8 CODE abGammaB[] = {
0x02,0x05,0x09,0x0D,0x11,0x15,0x19,0x1C,0x1F,0x22,0x24,0x27,0x29,0x2B,0x2E,0x2F,
0x31,0x33,0x35,0x36,0x38,0x39,0x3B,0x3C,0x3D,0x3F,0x40,0x41,0x42,0x43,0x44,0x46,
0x47,0x48,0x49,0x4A,0x4B,0x4B,0x4C,0x4D,0x4E,0x4F,0x50,0x50,0x51,0x52,0x53,0x54,
0x54,0x55,0x56,0x57,0x57,0x58,0x59,0x59,0x5A,0x5B,0x5B,0x5C,0x5D,0x5D,0x5E,0x5F,
0x5F,0x60,0x61,0x62,0x62,0x63,0x63,0x64,0x65,0x65,0x66,0x67,0x67,0x68,0x69,0x69,
0x6A,0x6A,0x6B,0x6C,0x6C,0x6D,0x6D,0x6E,0x6F,0x6F,0x70,0x70,0x71,0x72,0x72,0x73,
0x74,0x74,0x75,0x75,0x76,0x77,0x77,0x78,0x78,0x79,0x7A,0x7A,0x7B,0x7B,0x7C,0x7D,
0x7D,0x7E,0x7E,0x7F,0x80,0x80,0x81,0x81,0x82,0x82,0x83,0x84,0x84,0x85,0x85,0x86,
0x87,0x87,0x88,0x88,0x89,0x8A,0x8A,0x8B,0x8B,0x8C,0x8D,0x8D,0x8E,0x8E,0x8F,0x90,
0x90,0x91,0x91,0x92,0x93,0x93,0x94,0x95,0x95,0x96,0x96,0x97,0x98,0x98,0x99,0x9A,
0x9A,0x9B,0x9C,0x9C,0x9D,0x9E,0x9E,0x9F,0xA0,0xA0,0xA1,0xA1,0xA2,0xA3,0xA4,0xA4,
0xA5,0xA6,0xA6,0xA7,0xA8,0xA8,0xA9,0xAA,0xAB,0xAB,0xAC,0xAD,0xAE,0xAF,0xAF,0xB0,
0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF,
0xC0,0xC1,0xC2,0xC3,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCD,0xCE,0xCF,0xD0,0xD2,
0xD3,0xD4,0xD6,0xD7,0xD8,0xDA,0xDB,0xDC,0xDE,0xDF,0xE1,0xE2,0xE4,0xE5,0xE7,0xE8,
0xEA,0xEB,0xED,0xEE,0xF0,0xF1,0xF3,0xF4,0xF6,0xF8,0xF9,0xFA,0xFC,0xFD,0xFE,0xFF,
};
#else
extern UB8 CODE abGammaR[ 256 ];
extern UB8 CODE abGammaG[ 256 ];
extern UB8 CODE abGammaB[ 256 ];
#endif
#endif
/* ------------------------------------
Function Prototypes
------------------------------------ */
EXTERN void VP_BlankColor(BOOL fON);
#if (VP_DISPLAYMODE)
EXTERN void VP_DisplayMode(UB8 bDisplayMode);
#endif
EXTERN void VP_HardwareReset(void);
EXTERN void VP_Init(void);
#if (VP_SET_BLACKLEVEL)
EXTERN void VP_SetBlackLevel(UB8 bBlackLevel,UB8 bWhiteSlope,UB8 bBlackSlope,UB8 bWhiteStart,UB8 bBlackStart);
#endif
#if (VP_SET_BRIGHTNESS)
EXTERN void VP_SetBrightness(UB8 bBrightness);
#endif
#if (VP_SET_COLORSTANDARD)
EXTERN void VP_SetColorStandard(UB8 bCS_Mode);
#endif
#if (VP_SET_CONTRAST)
EXTERN void VP_SetContrast(UB8 bContrast);
#endif
#if (VP_SET_IMAGE_FILTER)
EXTERN void VP_SetImageFilter(UB8 bImageFilter);
#endif
#if (VP_SET_PWM_DUTY)
EXTERN void VP_SetPWM_DUTY(UB8 bPWM, UW16 wDUTY);
#endif
#if (VP_SET_PWM_FREQ)
EXTERN void VP_SetPWM_FREQ(UB8 bPWM, UW16 wFREQ);
#endif
#if (VP_SET_PWM_REF)
EXTERN void VP_SetPWM_REF(UB8 bPWM, UW16 wREF);
#endif
#if (VP_SET_TCON_MODE)
EXTERN void VP_SetTCON_Mode(UB8 bTCON_Mode);
#endif
#if (VP_SET_TESTPATTERN)
EXTERN void VP_SetTestPattern(UB8 bColorR, UB8 bColorG, UB8 bColorB, UB8 bPatternType, UB8 bMode);
#endif
//EXTERN void VP_WaitStdReady(void);
#endif /* _VP_H_ */
/* **********************************************************************
Description:
********************************************************************** */
/* %% End Of File %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */