www.pudn.com > usbold11.rar > usb-ohci.h
/*
* URB OHCI HCD (Host Controller Driver) for USB.
*
*(C) Copyright 1999 Roman Weissgaerber
*
* ohci-hcd.h
*
*/
#define MODSTR "ohci: "
static int cc_to_error[16] = {
/* mapping of the OHCI CC status to error codes */
#ifdef USB_ST_CRC /* status codes */
/* No Error */ USB_ST_NOERROR,
/* CRC Error */ USB_ST_CRC,
/* Bit Stuff */ USB_ST_BITSTUFF,
/* Data Togg */ USB_ST_CRC,
/* Stall */ USB_ST_STALL,
/* DevNotResp */ USB_ST_NORESPONSE,
/* PIDCheck */ USB_ST_BITSTUFF,
/* UnExpPID */ USB_ST_BITSTUFF,
/* DataOver */ USB_ST_DATAOVERRUN,
/* DataUnder */ USB_ST_DATAUNDERRUN,
/* reservd */ USB_ST_NORESPONSE,
/* reservd */ USB_ST_NORESPONSE,
/* BufferOver */ USB_ST_BUFFEROVERRUN,
/* BuffUnder */ USB_ST_BUFFERUNDERRUN,
/* Not Access */ USB_ST_NORESPONSE,
/* Not Access */ USB_ST_NORESPONSE
};
#else /* error codes */
/* No Error */ 0,
/* CRC Error */ -EILSEQ,
/* Bit Stuff */ -EPROTO,
/* Data Togg */ -EILSEQ,
/* Stall */ -EPIPE,
/* DevNotResp */ -ETIMEDOUT,
/* PIDCheck */ -EPROTO,
/* UnExpPID */ -EPROTO,
/* DataOver */ -EOVERFLOW,
/* DataUnder */ -EREMOTEIO,
/* reservd */ -ETIMEDOUT,
/* reservd */ -ETIMEDOUT,
/* BufferOver */ -ECOMM,
/* BuffUnder */ -ECOMM,
/* Not Access */ -ETIMEDOUT,
/* Not Access */ -ETIMEDOUT
};
#define USB_ST_URB_PENDING -EINPROGRESS
#endif
struct ed;
struct td;
/* for ED and TD structures */
/* ED States */
#define ED_NEW 0x00
#define ED_UNLINK 0x01
#define ED_OPER 0x02
#define ED_DEL 0x04
#define ED_URB_DEL 0x08
/* usb_ohci_ed */
typedef struct ed {
__u32 hwINFO;
__u32 hwTailP;
__u32 hwHeadP;
__u32 hwNextED;
struct ed * ed_prev;
__u8 int_period;
__u8 int_branch;
__u8 int_load;
__u8 int_interval;
__u8 state;
__u8 type;
__u16 last_iso;
struct ed * ed_rm_list;
} ed_t;
/* TD info field */
#define TD_CC 0xf0000000
#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
#define TD_EC 0x0C000000
#define TD_T 0x03000000
#define TD_T_DATA0 0x02000000
#define TD_T_DATA1 0x03000000
#define TD_T_TOGGLE 0x00000000
#define TD_R 0x00040000
#define TD_DI 0x00E00000
#define TD_DI_SET(X) (((X) & 0x07)<< 21)
#define TD_DP 0x00180000
#define TD_DP_SETUP 0x00000000
#define TD_DP_IN 0x00100000
#define TD_DP_OUT 0x00080000
#define TD_ISO 0x00010000
#define TD_DEL 0x00020000
/* CC Codes */
#define TD_CC_NOERROR 0x00
#define TD_CC_CRC 0x01
#define TD_CC_BITSTUFFING 0x02
#define TD_CC_DATATOGGLEM 0x03
#define TD_CC_STALL 0x04
#define TD_DEVNOTRESP 0x05
#define TD_PIDCHECKFAIL 0x06
#define TD_UNEXPECTEDPID 0x07
#define TD_DATAOVERRUN 0x08
#define TD_DATAUNDERRUN 0x09
#define TD_BUFFEROVERRUN 0x0C
#define TD_BUFFERUNDERRUN 0x0D
#define TD_NOTACCESSED 0x0F
#define MAXPSW 1
typedef struct td {
__u32 hwINFO;
__u32 hwCBP; /* Current Buffer Pointer */
__u32 hwNextTD; /* Next TD Pointer */
__u32 hwBE; /* Memory Buffer End Pointer */
__u16 hwPSW[MAXPSW];
__u8 type;
__u8 index;
struct ed * ed;
struct td * next_dl_td;
urb_t * urb;
} td_t;
/* TD types */
#define BULK 0x03
#define INT 0x01
#define CTRL 0x02
#define ISO 0x00
#define SEND 0x01
#define ST_ADDR 0x02
#define ADD_LEN 0x04
#define DEL 0x08
#define OHCI_ED_SKIP (1 << 14)
/*
* The HCCA (Host Controller Communications Area) is a 256 byte
* structure defined in the OHCI spec. that the host controller is
* told the base address of. It must be 256-byte aligned.
*/
#define NUM_INTS 32 /* part of the OHCI standard */
struct ohci_hcca {
__u32 int_table[NUM_INTS]; /* Interrupt ED table */
__u16 frame_no; /* current frame number */
__u16 pad1; /* set to 0 on each frame_no change */
__u32 done_head; /* info returned for an interrupt */
u8 reserved_for_hc[116];
} __attribute((aligned(256)));
/*
* Maximum number of root hub ports.
*/
#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
/*
* This is the structure of the OHCI controller's memory mapped I/O
* region. This is Memory Mapped I/O. You must use the readl() and
* writel() macros defined in asm/io.h to access these!!
*/
struct ohci_regs {
/* control and status registers */
__u32 revision;
__u32 control;
__u32 cmdstatus;
__u32 intrstatus;
__u32 intrenable;
__u32 intrdisable;
/* memory pointers */
__u32 hcca;
__u32 ed_periodcurrent;
__u32 ed_controlhead;
__u32 ed_controlcurrent;
__u32 ed_bulkhead;
__u32 ed_bulkcurrent;
__u32 donehead;
/* frame counters */
__u32 fminterval;
__u32 fmremaining;
__u32 fmnumber;
__u32 periodicstart;
__u32 lsthresh;
/* Root hub ports */
struct ohci_roothub_regs {
__u32 a;
__u32 b;
__u32 status;
__u32 portstatus[MAX_ROOT_PORTS];
} roothub;
} __attribute((aligned(32)));
/*
* cmdstatus register */
#define OHCI_CLF 0x02
#define OHCI_BLF 0x04
/*
* Interrupt register masks
*/
#define OHCI_INTR_SO (1)
#define OHCI_INTR_WDH (1 << 1)
#define OHCI_INTR_SF (1 << 2)
#define OHCI_INTR_RD (1 << 3)
#define OHCI_INTR_UE (1 << 4)
#define OHCI_INTR_FNO (1 << 5)
#define OHCI_INTR_RHSC (1 << 6)
#define OHCI_INTR_OC (1 << 30)
#define OHCI_INTR_MIE (1 << 31)
/*
* Control register masks
*/
#define OHCI_USB_RESET 0
#define OHCI_USB_RESUME (1 << 6)
#define OHCI_USB_OPER (2 << 6)
#define OHCI_USB_SUSPEND (3 << 6)
/* Virtual Root HUB */
struct virt_root_hub {
int devnum; /* Address of Root Hub endpoint */
void * urb;
void * int_addr;
int send;
int interval;
struct timer_list rh_int_timer;
};
/* destination of request */
#define RH_INTERFACE 0x01
#define RH_ENDPOINT 0x02
#define RH_OTHER 0x03
#define RH_CLASS 0x20
#define RH_VENDOR 0x40
/* Requests: bRequest << 8 | bmRequestType */
#define RH_GET_STATUS 0x0080
#define RH_CLEAR_FEATURE 0x0100
#define RH_SET_FEATURE 0x0300
#define RH_SET_ADDRESS 0x0500
#define RH_GET_DESCRIPTOR 0x0680
#define RH_SET_DESCRIPTOR 0x0700
#define RH_GET_CONFIGURATION 0x0880
#define RH_SET_CONFIGURATION 0x0900
#define RH_GET_STATE 0x0280
#define RH_GET_INTERFACE 0x0A80
#define RH_SET_INTERFACE 0x0B00
#define RH_SYNC_FRAME 0x0C80
/* Our Vendor Specific Request */
#define RH_SET_EP 0x2000
/* Hub port features */
#define RH_PORT_CONNECTION 0x00
#define RH_PORT_ENABLE 0x01
#define RH_PORT_SUSPEND 0x02
#define RH_PORT_OVER_CURRENT 0x03
#define RH_PORT_RESET 0x04
#define RH_PORT_POWER 0x08
#define RH_PORT_LOW_SPEED 0x09
#define RH_C_PORT_CONNECTION 0x10
#define RH_C_PORT_ENABLE 0x11
#define RH_C_PORT_SUSPEND 0x12
#define RH_C_PORT_OVER_CURRENT 0x13
#define RH_C_PORT_RESET 0x14
/* Hub features */
#define RH_C_HUB_LOCAL_POWER 0x00
#define RH_C_HUB_OVER_CURRENT 0x01
#define RH_DEVICE_REMOTE_WAKEUP 0x00
#define RH_ENDPOINT_STALL 0x01
#define RH_ACK 0x01
#define RH_REQ_ERR -1
#define RH_NACK 0x00
/* Root-Hub Register info */
#define RH_PS_CCS 0x00000001
#define RH_PS_PES 0x00000002
#define RH_PS_PSS 0x00000004
#define RH_PS_POCI 0x00000008
#define RH_PS_PRS 0x00000010
#define RH_PS_PPS 0x00000100
#define RH_PS_LSDA 0x00000200
#define RH_PS_CSC 0x00010000
#define RH_PS_PESC 0x00020000
#define RH_PS_PSSC 0x00040000
#define RH_PS_OCIC 0x00080000
#define RH_PS_PRSC 0x00100000
#define min(a,b) (((a)<(b))?(a):(b))
/* urb */
typedef struct
{
ed_t * ed;
__u16 length; // number of tds associated with this request
__u16 td_cnt; // number of tds already serviced
int state;
void * wait;
td_t * td[0]; // list pointer to all corresponding TDs associated with this request
} urb_priv_t;
#define URB_DEL 1
/*
* This is the full ohci controller description
*
* Note how the "proper" USB information is just
* a subset of what the full implementation needs. (Linus)
*/
typedef struct ohci {
struct ohci_hcca hcca; /* hcca */
int irq;
struct ohci_regs * regs; /* OHCI controller's memory */
struct list_head ohci_hcd_list; /* list of all ohci_hcd */
struct ohci * next; // chain of uhci device contexts
struct list_head urb_list; // list of all pending urbs
spinlock_t urb_list_lock; // lock to keep consistency
int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load ballancing)*/
ed_t * ed_rm_list[2]; /* lists of all endpoints to be removed */
ed_t * ed_bulktail; /* last endpoint of bulk list */
ed_t * ed_controltail; /* last endpoint of control list */
ed_t * ed_isotail; /* last endpoint of iso list */
int intrstatus;
__u32 hc_control; /* copy of the hc control reg */
struct usb_bus * bus;
struct usb_device * dev[128];
struct virt_root_hub rh;
} ohci_t;
#define NUM_TDS 0 /* num of preallocated transfer descriptors */
#define NUM_EDS 32 /* num of preallocated endpoint descriptors */
struct ohci_device {
ed_t ed[NUM_EDS];
int ed_cnt;
void * wait;
};
// #define ohci_to_usb(ohci) ((ohci)->usb)
#define usb_to_ohci(usb) ((struct ohci_device *)(usb)->hcpriv)
/* hcd */
/* endpoint */
static int ep_link(ohci_t * ohci, ed_t * ed);
static int ep_unlink(ohci_t * ohci, ed_t * ed);
static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned int pipe, int interval, int load);
static void ep_rm_ed(struct usb_device * usb_dev, ed_t * ed);
/* td */
static void td_fill(unsigned int info, void * data, int len, urb_t * urb, int type, int index);
static void td_submit_urb(urb_t * urb);
/* root hub */
static int rh_submit_urb(urb_t * urb);
static int rh_unlink_urb(urb_t * urb);
static int rh_init_int_timer(urb_t * urb);
#ifdef DEBUG
#define OHCI_FREE(x) kfree(x); printk("OHCI FREE: %d: %4x\n", -- __ohci_free_cnt, (unsigned int) x)
#define OHCI_ALLOC(x,size) (x) = kmalloc(size, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); printk("OHCI ALLO: %d: %4x\n", ++ __ohci_free_cnt,(unsigned int) x)
static int __ohci_free_cnt = 0;
#else
#define OHCI_FREE(x) kfree(x)
#define OHCI_ALLOC(x,size) (x) = kmalloc(size, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL)
#endif