www.pudn.com > tl16c554.rar > 16c554.h

#ifndef _16C554_H 
	#define _16C554_H 
	 
	sbit UART_RST = P3^1; 
 
 
	 
	/******************************************************/ 
	/*	特殊功能寄存器地址定义                            */ 
	/******************************************************/ 
	 
	#define RBR 0X00      	//receiver-buffer register             
	#define THR 0X00	 	//transmitter-holding register 
	#define DLL 0X00 
	#define DLM 0X80 
	#define IER 0X80		//interrupt-enable register 
	#define FCR 0X40		//FIFO-control register 
	#define IIR 0X40		//interrupt-identification register 
	#define LCR 0XC0		//line-control register 
	#define MCR 0X20		//modem-control register 
	#define LSR 0Xa0		//line-status register 
	#define MSR 0X60		//modem-status register 
	#define SCR 0Xe0  		//scratchpad register 
	 
	#define UA_ADDR     0XC700 
	#define UA_RBR XBYTE[UA_ADDR+RBR]		//receiver-buffer register 
	#define UA_THR XBYTE[UA_ADDR+THR]		//transmitter-holding register 
	#define UA_DLL XBYTE[UA_ADDR+DLL] 
	#define UA_DLM XBYTE[UA_ADDR+DLM] 
	#define UA_IER XBYTE[UA_ADDR+IER]		//interrupt-enable register 
	#define UA_FCR XBYTE[UA_ADDR+FCR]		//FIFO-control register 
	#define UA_IIR XBYTE[UA_ADDR+IIR]		//interrupt-identification register 
	#define UA_LCR XBYTE[UA_ADDR+LCR]		//line-control register 
	#define UA_MCR XBYTE[UA_ADDR+MCR]		//modem-control register 
	#define UA_LSR XBYTE[UA_ADDR+LSR]		//line-status register 
	#define UA_MSR XBYTE[UA_ADDR+MSR]		//modem-status register 
	#define UA_SCR XBYTE[UA_ADDR+SCR]		//scratchpad register 
	 
	#define UB_ADDR     0XBB00 
	#define UB_RBR XBYTE[UB_ADDR+RBR]		//receiver-buffer register 
	#define UB_THR XBYTE[UB_ADDR+THR]		//transmitter-holding register 
	#define UB_DLL XBYTE[UB_ADDR+DLL] 
	#define UB_DLM XBYTE[UB_ADDR+DLM] 
	#define UB_IER XBYTE[UB_ADDR+IER]		//interrupt-enable register 
	#define UB_FCR XBYTE[UB_ADDR+FCR]		//FIFO-control register 
	#define UB_IIR XBYTE[UB_ADDR+IIR]		//interrupt-identification register 
	#define UB_LCR XBYTE[UB_ADDR+LCR]		//line-control register 
	#define UB_MCR XBYTE[UB_ADDR+MCR]		//modem-control register 
	#define UB_LSR XBYTE[UB_ADDR+LSR]		//line-status register 
	#define UB_MSR XBYTE[UB_ADDR+MSR]		//modem-status register 
	#define UB_SCR XBYTE[UB_ADDR+SCR]		//scratchpad register 
	 
	#define UC_ADDR     0XAD00 
	#define UC_RBR XBYTE[UC_ADDR+RBR]		//receiver-buffer register 
	#define UC_THR XBYTE[UC_ADDR+THR]		//transmitter-holding register 
	#define UC_DLL XBYTE[UC_ADDR+DLL] 
	#define UC_DLM XBYTE[UC_ADDR+DLM] 
	#define UC_IER XBYTE[UC_ADDR+IER]		//interrupt-enable register 
	#define UC_FCR XBYTE[UC_ADDR+FCR]		//FIFO-control register 
	#define UC_IIR XBYTE[UC_ADDR+IIR]		//interrupt-identification register 
	#define UC_LCR XBYTE[UC_ADDR+LCR]		//line-control register 
	#define UC_MCR XBYTE[UC_ADDR+MCR]		//modem-control register 
	#define UC_LSR XBYTE[UC_ADDR+LSR]		//line-status register 
	#define UC_MSR XBYTE[UC_ADDR+MSR]		//modem-status register 
	#define UC_SCR XBYTE[UC_ADDR+SCR]		//scratchpad register 
	 
	#define UD_ADDR     0X9E00 
	#define UD_RBR XBYTE[UD_ADDR+RBR]		//receiver-buffer register 
	#define UD_THR XBYTE[UD_ADDR+THR]		//transmitter-holding register 
	#define UD_DLL XBYTE[UD_ADDR+DLL] 
	#define UD_DLM XBYTE[UD_ADDR+DLM] 
	#define UD_IER XBYTE[UD_ADDR+IER]		//interrupt-enable register 
	#define UD_FCR XBYTE[UD_ADDR+FCR]		//FIFO-control register 
	#define UD_IIR XBYTE[UD_ADDR+IIR]		//interrupt-identification register 
	#define UD_LCR XBYTE[UD_ADDR+LCR]		//line-control register 
	#define UD_MCR XBYTE[UD_ADDR+MCR]		//modem-control register 
	#define UD_LSR XBYTE[UD_ADDR+LSR]		//line-status register 
	#define UD_MSR XBYTE[UD_ADDR+MSR]		//modem-status register 
	#define UD_SCR XBYTE[UD_ADDR+SCR]		//scratchpad register 
	 
	#define U_READ_STATUS XBYTE[0XDFFF]     //the address of the reading status from tl16c554  
	 
	//config FCR 
	#define FCR_CONFIG1		0X87            //ENABLE FIFO, 
											//CLEAR FIFO(receive and transmit FIFO) 
											//Triggle Level = 8(Bytes) 
	 
	//config IER 
	#define IER_CONFIG1     0X03           	// 
										   	// 
	 
	//config LCR 
	#define LCR_CONFIG1     0x03            //8 Bytes, 1 Stop bit, No Parity 
	 
	//config Bsp 
	#define U_CLOCK         3686400L 
	#define BAND_A          9600L 
	#define BAND_B          4800L 
	#define BAND_C          4800L 
	#define BAND_D          9600L 
	#define DLL_A           (U_CLOCK/BAND_A/16) 
	#define DLM_A			((U_CLOCK/BAND_A/16)>>8)  
	#define DLL_B           (U_CLOCK/BAND_B/16) 
	#define DLM_B			((U_CLOCK/BAND_B/16)>>8)  
	#define DLL_C           (U_CLOCK/BAND_C/16) 
	#define DLM_C			((U_CLOCK/BAND_C/16)>>8)  
	#define DLL_D           (U_CLOCK/BAND_D/16) 
	#define DLM_D			((U_CLOCK/BAND_D/16)>>8) 	 
	 
	//config MCR 
	#define MCR_CONFIG1      0x08           //Enable extern serial channel interrupt 
	 
	/* 
	******************************************************************************************** 
	*/ 
	#define ENABLE	YES 
	#define DISABLE NO 
	//各串口使能定义 
	#define	UARTA	DISABLE 
	#define UARTB	DISABLE 
	#define UARTC	DISABLE 
	#define UARTD	DISABLE 
	//串口任务参数定义 
	#define UARTA_TX	0X01 
	#define UARTA_TX_C	0XFE 
	#define UARTA_RX	0X02 
	#define UARTA_RX_C	0XFD 
	#define UARTB_TX	0X04 
	#define UARTB_TX_C	0XFB 
	#define UARTB_RX	0X08 
	#define UARTB_RX_C	0XF7 
	#define UARTC_TX	0X10 
	#define UARTC_TX_C	0XEF 
	#define UARTC_RX    0X20 
	#define UARTC_RX_C	0XDF 
	#define UARTD_TX    0X40 
	#define UARTD_TX_C	0XBF 
	#define UARTD_RX	0X80 
	#define UARTD_RX_C	0X7F 
	 
	// 
	#define UA_TX		0X01 
	#define UA_TX_CLEAR	0XFE 
 
	#define UB_TX		0X02 
	#define UB_TX_CLEAR	0XFB 
 
	#define UC_TX		0X04 
	#define UC_TX_CLEAR	0XFB 
 
	#define UD_TX		0X08 
	#define UD_TX_CLEAR	0XF7 
 
	 
#endif