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--dffpipe WIDTH=8 clock clrn d q 
--VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END 
 
 
--  Copyright (C) 1988-2005 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
 
--synthesis_resources = lut 8  
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF"; 
 
SUBDESIGN dffpipe_4l2 
(  
	clock	:	input; 
	clrn	:	input; 
	d[7..0]	:	input; 
	q[7..0]	:	output; 
)  
VARIABLE  
	dffe8a[7..0] : dffe; 
	ena	: NODE; 
	prn	: NODE; 
	sclr	: NODE; 
 
BEGIN  
	dffe8a[].CLK = clock; 
	dffe8a[].CLRN = clrn; 
	dffe8a[].D = (d[] & (! sclr)); 
	dffe8a[].ENA = ena; 
	dffe8a[].PRN = prn; 
	ena = VCC; 
	prn = VCC; 
	q[] = dffe8a[].Q; 
	sclr = GND; 
END; 
--VALID FILE