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--alt_ded_mult_y CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" dedicated_multiplier_circuitry="YES" device_family="Cyclone II" dsp_block_balancing="Auto" extra_latency=0 input_reg_a="UNREGISTERED" input_reg_b="UNREGISTERED" output_aclr="ACLR0" output_reg="CLOCK0" pipeline_reg="UNREGISTERED" representation_a="UNSIGNED" representation_b="UNSIGNED" sub_dedicated_multiplier_circuitry="YES" width_a=16 width_b=16 aclr clock dataa datab ena result 
--VERSION_BEGIN 5.0 cbx_alt_ded_mult_y 2005:03:29:13:57:02:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_padd 2005:04:14:12:08:54:SJ cbx_parallel_add 2003:11:11:15:26:08:SJ cbx_stratix 2005:11:01:14:36:46:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END 
 
 
--  Copyright (C) 1988-2005 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
FUNCTION cycloneii_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb) 
WITH ( 	dataa_clock,	dataa_width,	datab_clock,	datab_width,	signa_clock,	signb_clock)  
RETURNS ( dataout[dataa_width+datab_width-1..0]); 
PARAMETERS 
( 
	dataa_width = 0 
); 
FUNCTION cycloneii_mac_out (aclr, clk, dataa[dataa_width-1..0], ena) 
WITH ( 	dataa_width,	output_clock)  
RETURNS ( dataout[dataa_width-1..0]); 
FUNCTION dffpipe_qv5 (d[31..0]) 
RETURNS ( q[31..0]); 
 
--synthesis_resources = dsp_9bit 2  
SUBDESIGN ded_mult_2o81 
(  
	aclr[3..0]	:	input; 
	clock[3..0]	:	input; 
	dataa[15..0]	:	input; 
	datab[15..0]	:	input; 
	ena[3..0]	:	input; 
	result[31..0]	:	output; 
	scanouta[15..0]	:	output; 
	scanoutb[15..0]	:	output; 
	signa_out	:	output; 
	signb_out	:	output; 
)  
VARIABLE  
	mac_mult2 : cycloneii_mac_mult 
		WITH ( 
			dataa_width = 16, 
			datab_width = 16 
		); 
	mac_out3 : cycloneii_mac_out 
		WITH ( 
			dataa_width = 32, 
			output_clock = "0" 
		); 
	pre_result : dffpipe_qv5; 
	gnd_wire[0..0]	: WIRE; 
	x_dataa[15..0]	: WIRE; 
	x_datab[15..0]	: WIRE; 
	x_signa[0..0]	: WIRE; 
	x_signb[0..0]	: WIRE; 
 
BEGIN  
	mac_mult2.aclr = aclr[0..0]; 
	mac_mult2.clk = clock[0..0]; 
	mac_mult2.dataa[] = ( x_dataa[]); 
	mac_mult2.datab[] = ( x_datab[]); 
	mac_mult2.ena = ena[0..0]; 
	mac_mult2.signa = x_signa[]; 
	mac_mult2.signb = x_signb[]; 
	mac_out3.aclr = aclr[0..0]; 
	mac_out3.clk = clock[0..0]; 
	mac_out3.dataa[] = ( mac_mult2.dataout[31..0]); 
	mac_out3.ena = ena[0..0]; 
	pre_result.d[31..0] = mac_out3.dataout[31..0]; 
	gnd_wire[] = B"0"; 
	result[] = pre_result.q[]; 
	scanouta[] = dataa[]; 
	scanoutb[] = datab[]; 
	signa_out = B"0"; 
	signb_out = B"0"; 
	x_dataa[] = dataa[]; 
	x_datab[] = datab[]; 
	x_signa[] = B"0"; 
	x_signb[] = B"0"; 
END; 
--VALID FILE