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--altsyncram ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="NORMAL" CYCLONEII_SAFE_WRITE="NO_CHANGE" DEVICE_FAMILY="Cyclone II" INIT_FILE="bht_ram.mif" MAXIMUM_DEPTH=0 NUMWORDS_A=256 NUMWORDS_B=256 OPERATION_MODE="BIDIR_DUAL_PORT" RAM_BLOCK_TYPE="AUTO" WIDTH_A=2 WIDTH_B=2 WIDTHAD_A=8 WIDTHAD_B=8 WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 clocken0 data_a data_b q_a wren_a wren_b --VERSION_BEGIN 5.0 cbx_altsyncram 2005:11:01:19:33:48:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:11:01:14:36:46:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END -- Copyright (C) 1988-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. PARAMETERS ( PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_DATA_WIDTH = 1, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_DATA_WIDTH = 1 ); FUNCTION cycloneii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe) WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH, PORT_A_BYTE_ENABLE_MASK_WIDTH, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE) RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); --synthesis_resources = M4K 1 SUBDESIGN altsyncram_iab1 ( address_a[7..0] : input; address_b[7..0] : input; clock0 : input; clock1 : input; clocken0 : input; data_a[1..0] : input; data_b[1..0] : input; q_a[1..0] : output; q_b[1..0] : output; wren_a : input; wren_b : input; ) VARIABLE ram_block2a0 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "bht_ram.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 8, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 255, PORT_A_LOGICAL_RAM_DEPTH = 256, PORT_A_LOGICAL_RAM_WIDTH = 2, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 8, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 255, PORT_B_LOGICAL_RAM_DEPTH = 256, PORT_B_LOGICAL_RAM_WIDTH = 2, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a1 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "bht_ram.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 8, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 1, PORT_A_LAST_ADDRESS = 255, PORT_A_LOGICAL_RAM_DEPTH = 256, PORT_A_LOGICAL_RAM_WIDTH = 2, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 8, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 1, PORT_B_LAST_ADDRESS = 255, PORT_B_LOGICAL_RAM_DEPTH = 256, PORT_B_LOGICAL_RAM_WIDTH = 2, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); address_a_wire[7..0] : WIRE; address_b_wire[7..0] : WIRE; BEGIN ram_block2a[1..0].clk0 = clock0; ram_block2a[1..0].clk1 = clock1; ram_block2a[1..0].ena0 = clocken0; ram_block2a[0].portaaddr[] = ( address_a_wire[7..0]); ram_block2a[1].portaaddr[] = ( address_a_wire[7..0]); ram_block2a[0].portadatain[] = ( data_a[0..0]); ram_block2a[1].portadatain[] = ( data_a[1..1]); ram_block2a[1..0].portawe = wren_a; ram_block2a[0].portbaddr[] = ( address_b_wire[7..0]); ram_block2a[1].portbaddr[] = ( address_b_wire[7..0]); ram_block2a[0].portbdatain[] = ( data_b[0..0]); ram_block2a[1].portbdatain[] = ( data_b[1..1]); ram_block2a[1..0].portbrewe = wren_b; address_a_wire[] = address_a[]; address_b_wire[] = address_b[]; q_a[] = ( ram_block2a[1..0].portadataout[0..0]); q_b[] = ( ram_block2a[1..0].portbdataout[0..0]); END; --VALID FILE