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--altsyncram ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_B="BYPASS" DEVICE_FAMILY="Cyclone II" OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="CLEAR1" OUTDATA_REG_B="CLOCK1" RAM_BLOCK_TYPE="M4K" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 WIDTHAD_B=8 aclr1 address_a address_b addressstall_b clock0 clock1 clocken1 data_a q_b wren_a 
--VERSION_BEGIN 5.0 cbx_altsyncram 2005:11:01:19:33:48:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:11:01:14:36:46:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END 
 
 
--  Copyright (C) 1988-2005 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
FUNCTION altsyncram_9691 (aclr1, address_a[7..0], address_b[7..0], addressstall_a, clock0, clock1, clocken0, data_a[15..0], data_b[15..0], wren_a, wren_b) 
RETURNS ( q_a[15..0], q_b[15..0]); 
 
--synthesis_resources = M4K 1  
SUBDESIGN altsyncram_41u 
(  
	aclr1	:	input; 
	address_a[7..0]	:	input; 
	address_b[7..0]	:	input; 
	addressstall_b	:	input; 
	clock0	:	input; 
	clock1	:	input; 
	clocken1	:	input; 
	data_a[15..0]	:	input; 
	q_b[15..0]	:	output; 
	wren_a	:	input; 
)  
VARIABLE  
	altsyncram3 : altsyncram_9691; 
 
BEGIN  
	altsyncram3.aclr1 = aclr1; 
	altsyncram3.address_a[] = address_b[]; 
	altsyncram3.address_b[] = address_a[]; 
	altsyncram3.addressstall_a = addressstall_b; 
	altsyncram3.clock0 = clock1; 
	altsyncram3.clock1 = clock0; 
	altsyncram3.clocken0 = clocken1; 
	altsyncram3.data_a[] = B"1111111111111111"; 
	altsyncram3.data_b[] = data_a[]; 
	altsyncram3.wren_a = B"0"; 
	altsyncram3.wren_b = wren_a; 
	q_b[] = altsyncram3.q_a[]; 
END; 
--VALID FILE