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--altsyncram ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="NORMAL" CYCLONEII_SAFE_WRITE="NO_CHANGE" DEVICE_FAMILY="Cyclone II" MAXIMUM_DEPTH=0 NUMWORDS_A=1024 NUMWORDS_B=1024 OPERATION_MODE="BIDIR_DUAL_PORT" RAM_BLOCK_TYPE="AUTO" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=10 WIDTHAD_B=10 WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 clocken0 data_a data_b q_a wren_a wren_b --VERSION_BEGIN 5.0 cbx_altsyncram 2005:11:01:19:33:48:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:11:01:14:36:46:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END -- Copyright (C) 1988-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. PARAMETERS ( PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_DATA_WIDTH = 1, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_DATA_WIDTH = 1 ); FUNCTION cycloneii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe) WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH, PORT_A_BYTE_ENABLE_MASK_WIDTH, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE) RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); --synthesis_resources = M4K 8 SUBDESIGN altsyncram_3e91 ( address_a[9..0] : input; address_b[9..0] : input; clock0 : input; clock1 : input; clocken0 : input; data_a[31..0] : input; data_b[31..0] : input; q_a[31..0] : output; q_b[31..0] : output; wren_a : input; wren_b : input; ) VARIABLE ram_block2a0 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 0, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a1 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 1, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 1, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a2 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 2, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 2, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a3 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 3, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 3, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a4 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 4, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 4, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a5 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 5, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 5, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a6 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 6, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 6, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a7 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 7, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 7, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a8 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 8, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 8, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a9 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 9, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 9, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a10 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 10, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 10, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a11 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 11, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 11, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a12 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 12, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 12, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a13 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 13, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 13, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a14 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 14, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 14, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a15 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 15, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 15, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a16 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 16, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 16, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a17 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 17, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 17, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a18 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 18, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 18, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a19 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 19, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 19, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a20 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 20, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 20, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a21 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 21, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 21, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a22 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 22, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 22, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a23 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 23, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 23, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a24 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 24, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 24, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a25 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 25, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 25, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a26 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 26, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 26, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a27 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 27, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 27, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a28 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 28, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 28, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a29 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 29, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 29, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a30 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 30, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 30, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); ram_block2a31 : cycloneii_ram_block WITH ( CONNECTIVITY_CHECKING = "OFF", LOGICAL_RAM_NAME = "ALTSYNCRAM", MIXED_PORT_FEED_THROUGH_MODE = "dont_care", OPERATION_MODE = "bidir_dual_port", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 31, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 32, PORT_B_ADDRESS_CLOCK = "clock1", PORT_B_ADDRESS_WIDTH = 10, PORT_B_DATA_IN_CLOCK = "clock1", PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off", PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off", PORT_B_FIRST_ADDRESS = 0, PORT_B_FIRST_BIT_NUMBER = 31, PORT_B_LAST_ADDRESS = 1023, PORT_B_LOGICAL_RAM_DEPTH = 1024, PORT_B_LOGICAL_RAM_WIDTH = 32, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1", RAM_BLOCK_TYPE = "auto" ); address_a_wire[9..0] : WIRE; address_b_wire[9..0] : WIRE; BEGIN ram_block2a[31..0].clk0 = clock0; ram_block2a[31..0].clk1 = clock1; ram_block2a[31..0].ena0 = clocken0; ram_block2a[0].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[1].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[2].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[3].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[4].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[5].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[6].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[7].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[8].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[9].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[10].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[11].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[12].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[13].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[14].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[15].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[16].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[17].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[18].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[19].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[20].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[21].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[22].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[23].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[24].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[25].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[26].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[27].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[28].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[29].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[30].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[31].portaaddr[] = ( address_a_wire[9..0]); ram_block2a[0].portadatain[] = ( data_a[0..0]); ram_block2a[1].portadatain[] = ( data_a[1..1]); ram_block2a[2].portadatain[] = ( data_a[2..2]); ram_block2a[3].portadatain[] = ( data_a[3..3]); ram_block2a[4].portadatain[] = ( data_a[4..4]); ram_block2a[5].portadatain[] = ( data_a[5..5]); ram_block2a[6].portadatain[] = ( data_a[6..6]); ram_block2a[7].portadatain[] = ( data_a[7..7]); ram_block2a[8].portadatain[] = ( data_a[8..8]); ram_block2a[9].portadatain[] = ( data_a[9..9]); ram_block2a[10].portadatain[] = ( data_a[10..10]); ram_block2a[11].portadatain[] = ( data_a[11..11]); ram_block2a[12].portadatain[] = ( data_a[12..12]); ram_block2a[13].portadatain[] = ( data_a[13..13]); ram_block2a[14].portadatain[] = ( data_a[14..14]); ram_block2a[15].portadatain[] = ( data_a[15..15]); ram_block2a[16].portadatain[] = ( data_a[16..16]); ram_block2a[17].portadatain[] = ( data_a[17..17]); ram_block2a[18].portadatain[] = ( data_a[18..18]); ram_block2a[19].portadatain[] = ( data_a[19..19]); ram_block2a[20].portadatain[] = ( data_a[20..20]); ram_block2a[21].portadatain[] = ( data_a[21..21]); ram_block2a[22].portadatain[] = ( data_a[22..22]); ram_block2a[23].portadatain[] = ( data_a[23..23]); ram_block2a[24].portadatain[] = ( data_a[24..24]); ram_block2a[25].portadatain[] = ( data_a[25..25]); ram_block2a[26].portadatain[] = ( data_a[26..26]); ram_block2a[27].portadatain[] = ( data_a[27..27]); ram_block2a[28].portadatain[] = ( data_a[28..28]); ram_block2a[29].portadatain[] = ( data_a[29..29]); ram_block2a[30].portadatain[] = ( data_a[30..30]); ram_block2a[31].portadatain[] = ( data_a[31..31]); ram_block2a[31..0].portawe = wren_a; ram_block2a[0].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[1].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[2].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[3].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[4].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[5].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[6].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[7].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[8].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[9].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[10].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[11].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[12].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[13].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[14].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[15].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[16].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[17].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[18].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[19].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[20].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[21].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[22].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[23].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[24].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[25].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[26].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[27].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[28].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[29].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[30].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[31].portbaddr[] = ( address_b_wire[9..0]); ram_block2a[0].portbdatain[] = ( data_b[0..0]); ram_block2a[1].portbdatain[] = ( data_b[1..1]); ram_block2a[2].portbdatain[] = ( data_b[2..2]); ram_block2a[3].portbdatain[] = ( data_b[3..3]); ram_block2a[4].portbdatain[] = ( data_b[4..4]); ram_block2a[5].portbdatain[] = ( data_b[5..5]); ram_block2a[6].portbdatain[] = ( data_b[6..6]); ram_block2a[7].portbdatain[] = ( data_b[7..7]); ram_block2a[8].portbdatain[] = ( data_b[8..8]); ram_block2a[9].portbdatain[] = ( data_b[9..9]); ram_block2a[10].portbdatain[] = ( data_b[10..10]); ram_block2a[11].portbdatain[] = ( data_b[11..11]); ram_block2a[12].portbdatain[] = ( data_b[12..12]); ram_block2a[13].portbdatain[] = ( data_b[13..13]); ram_block2a[14].portbdatain[] = ( data_b[14..14]); ram_block2a[15].portbdatain[] = ( data_b[15..15]); ram_block2a[16].portbdatain[] = ( data_b[16..16]); ram_block2a[17].portbdatain[] = ( data_b[17..17]); ram_block2a[18].portbdatain[] = ( data_b[18..18]); ram_block2a[19].portbdatain[] = ( data_b[19..19]); ram_block2a[20].portbdatain[] = ( data_b[20..20]); ram_block2a[21].portbdatain[] = ( data_b[21..21]); ram_block2a[22].portbdatain[] = ( data_b[22..22]); ram_block2a[23].portbdatain[] = ( data_b[23..23]); ram_block2a[24].portbdatain[] = ( data_b[24..24]); ram_block2a[25].portbdatain[] = ( data_b[25..25]); ram_block2a[26].portbdatain[] = ( data_b[26..26]); ram_block2a[27].portbdatain[] = ( data_b[27..27]); ram_block2a[28].portbdatain[] = ( data_b[28..28]); ram_block2a[29].portbdatain[] = ( data_b[29..29]); ram_block2a[30].portbdatain[] = ( data_b[30..30]); ram_block2a[31].portbdatain[] = ( data_b[31..31]); ram_block2a[31..0].portbrewe = wren_b; address_a_wire[] = address_a[]; address_b_wire[] = address_b[]; q_a[] = ( ram_block2a[31..0].portadataout[0..0]); q_b[] = ( ram_block2a[31..0].portbdataout[0..0]); END; --VALID FILE