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--altsyncram ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" MAXIMUM_DEPTH=0 NUMWORDS_A=1024 NUMWORDS_B=1024 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=10 WIDTHAD_B=10 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
--VERSION_BEGIN 5.0 cbx_altsyncram 2005:11:01:19:33:48:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:11:01:14:36:46:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
-- Copyright (C) 1988-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION altsyncram_3e91 (address_a[9..0], address_b[9..0], clock0, clock1, clocken0, data_a[31..0], data_b[31..0], wren_a, wren_b)
RETURNS ( q_a[31..0], q_b[31..0]);
--synthesis_resources = M4K 8
SUBDESIGN altsyncram_0q21
(
address_a[9..0] : input;
address_b[9..0] : input;
clock0 : input;
clock1 : input;
clocken1 : input;
data_a[31..0] : input;
q_b[31..0] : output;
wren_a : input;
)
VARIABLE
altsyncram1 : altsyncram_3e91;
BEGIN
altsyncram1.address_a[] = address_b[];
altsyncram1.address_b[] = address_a[];
altsyncram1.clock0 = clock1;
altsyncram1.clock1 = clock0;
altsyncram1.clocken0 = clocken1;
altsyncram1.data_a[] = B"11111111111111111111111111111111";
altsyncram1.data_b[] = data_a[];
altsyncram1.wren_a = B"0";
altsyncram1.wren_b = wren_a;
q_b[] = altsyncram1.q_a[];
END;
--VALID FILE