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--dffpipe WIDTH=8 clock clrn d q --VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:11:01:19:33:48:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:10:21:13:37:44:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:11:01:14:36:46:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END -- Copyright (C) 1988-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. FUNCTION dffpipe_3l2 (clock, clrn, d[7..0]) RETURNS ( q[7..0]); --synthesis_resources = lut 8 OPTIONS ALTERA_INTERNAL_OPTION = "X_ON_VIOLATION_OPTION=OFF"; SUBDESIGN alt_synch_pipe_3l2 ( clock : input; clrn : input; d[7..0] : input; q[7..0] : output; ) VARIABLE dffpipe5 : dffpipe_3l2; BEGIN dffpipe5.clock = clock; dffpipe5.clrn = clrn; dffpipe5.d[] = d[]; q[] = dffpipe5.q[]; END; --VALID FILE