www.pudn.com > SD_Card_Audio.rar > AUD_FULL.v

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// synthesis translate_off 
`timescale 1ns / 100ps 
// synthesis translate_on 
module AUD_FULL ( 
                  // inputs: 
                   address, 
                   clk, 
                   in_port, 
                   reset_n, 
 
                  // outputs: 
                   readdata 
                ); 
 
  output           readdata; 
  input   [  1: 0] address; 
  input            clk; 
  input            in_port; 
  input            reset_n; 
 
  wire             clk_en; 
  wire             data_in; 
  wire             read_mux_out; 
  reg              readdata; 
  assign clk_en = 1; 
  //s1, which is an e_avalon_slave 
  assign read_mux_out = {1 {(address == 0)}} & data_in; 
  always @(posedge clk or negedge reset_n) 
    begin 
      if (reset_n == 0) 
          readdata <= 0; 
      else if (clk_en) 
          readdata <= read_mux_out; 
    end 
 
 
  assign data_in = in_port; 
 
 
endmodule