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-- File Name: pcic_pk.tdf -- Function : This design will take care of all parity checking operation -- Author : Ziad M. Abu-Lebdeh -- Rev History -- 2/98 Initial Entry -- -- $History: pcic_pk.tdf $ -- -- ***************** Version 66 ***************** -- User: Afauria Date: 6/15/99 Time: 6:35p -- Updated in $/MegaCore/HandOff/45/source/src -- -- ***************** Version 65 ***************** -- User: Otan Date: 6/14/99 Time: 1:15p -- Updated in $/MegaCore/HandOff/45/source/src -- Optimized frame_or and req64_or for setup -- -- ***************** Version 64 ***************** -- User: Otan Date: 5/11/99 Time: 4:14p -- Updated in $/MegaCore/HandOff/45/source/src -- DAC back; after version1.01 -- -- ***************** Version 62 ***************** -- User: Otan Date: 3/14/99 Time: 8:59a -- Updated in $/MegaCore/HandOff/45/source/src -- pre1.0-2 -- -- ***************** Version 61 ***************** -- User: Otan Date: 3/03/99 Time: 2:48p -- Updated in $/MegaCore/HandOff/45/source/src -- 66 mhz optimization. Need to look at double cascade on irdy_or_not and -- trdy_or_not. -- -- ***************** Version 60 ***************** -- User: Otan Date: 3/02/99 Time: 5:38p -- Updated in $/MegaCore/HandOff/45/source/src -- -- ***************** Version 59 ***************** -- User: Otan Date: 3/02/99 Time: 2:23p -- Updated in $/MegaCore/HandOff/45/source/src -- 66 MHz Optimization -- -- ***************** Version 58 ***************** -- User: Otan Date: 3/02/99 Time: 10:24a -- Updated in $/MegaCore/HandOff/45/source/src -- Simulations work -- -- ***************** Version 57 ***************** -- User: Otan Date: 2/26/99 Time: 6:05p -- Updated in $/MegaCore/HandOff/45/source/src -- Fixed fast_back-to-back -- -- ***************** Version 56 ***************** -- User: Otan Date: 2/26/99 Time: 11:53a -- Updated in $/MegaCore/HandOff/45/source/src -- MS_REQ Optimization fixed -- -- ***************** Version 54 ***************** -- User: Otan Date: 2/17/99 Time: 5:13p -- Updated in $/MegaCore/HandOff/45/source/src -- -- ***************** Version 53 ***************** -- User: Otan Date: 2/16/99 Time: 7:56p -- Updated in $/MegaCore/HandOff/45/source/src -- master write simulations -- -- ***************** Version 52 ***************** -- User: Otan Date: 2/09/99 Time: 8:58a -- Updated in $/MegaCore/HandOff/45/source/src -- Updated for Master Read simulations. 2/9/99 -- -- ***************** Version 51 ***************** -- User: Otan Date: 2/05/99 Time: 11:11a -- Updated in $/MegaCore/HandOff/45/source/src -- Fixed master abort -- -- ***************** Version 50 ***************** -- User: Otan Date: 2/02/99 Time: 2:11p -- Updated in $/MegaCore/HandOff/45/source/src -- -- ***************** Version 49 ***************** -- User: Otan Date: 2/02/99 Time: 1:07p -- Updated in $/MegaCore/HandOff/45/source/src -- Updated master parity error -- -- ***************** Version 48 ***************** -- User: Otan Date: 1/29/99 Time: 11:59a -- Updated in $/MegaCore/HandOff/45/source/src -- Been Optimized to meet 33MHz performance. -- -- ***************** Version 47 ***************** -- User: Otan Date: 1/28/99 Time: 8:31a -- Updated in $/MegaCore/HandOff/45/source/src -- Master and Target Optimizations. These files are before we changed -- ador_hi_dena in pcic_t.tdf. -- -- ***************** Version 46 ***************** -- User: Otan Date: 1/27/99 Time: 9:08a -- Updated in $/MegaCore/HandOff/45/source/src -- Target and Master Optimizations -- -- ***************** Version 45 ***************** -- User: Otan Date: 1/25/99 Time: 10:43a -- Updated in $/MegaCore/HandOff/45/source/src -- Target Optimization -- -- ***************** Version 44 ***************** -- User: Otan Date: 1/21/99 Time: 4:27p -- Updated in $/MegaCore/HandOff/45/source/src -- Target Write and Read have been extensively simulated -- -- ***************** Version 43 ***************** -- User: Otan Date: 12/24/98 Time: 12:49p -- Updated in $/MegaCore/HandOff/45/source/src -- -- ***************** Version 42 ***************** -- User: Otan Date: 12/22/98 Time: 4:27p -- Updated in $/MegaCore/HandOff/45/source/src -- Fixing wait states for each data phase -- -- ***************** Version 41 ***************** -- User: Otan Date: 12/16/98 Time: 7:33a -- Updated in $/MegaCore/HandOff/45/source/src -- for beta release -- -- ***************** Version 39 ***************** -- User: Otan Date: 12/16/98 Time: 7:01a -- Updated in $/MegaCore/HandOff/45/source/src -- for beta release -- -- ***************** Version 37 ***************** -- User: Otan Date: 12/15/98 Time: 9:29p -- Updated in $/MegaCore/HandOff/45/source/src -- -- ***************** Version 36 ***************** -- User: Otan Date: 12/14/98 Time: 11:17p -- Updated in $/MegaCore/HandOff/45/source/src -- -- ***************** Version 35 ***************** -- User: Otan Date: 12/12/98 Time: 2:55p -- Updated in $/MegaCore/HandOff/45/source/src -- Added a new parity tree for the address phase. Parity seems to be -- working, Needs further simulations. -- -- ***************** Version 34 ***************** -- User: Ziada Date: 12/11/98 Time: 9:23a -- Updated in $/MegaCore/HandOff/45/source/src -- Added cascade chain on perr and serr -- -- ***************** Version 32 ***************** -- User: Otan Date: 12/08/98 Time: 4:59p -- Updated in $/MegaCore/HandOff/45/source/src -- -- ***************** Version 31 ***************** -- User: Otan Date: 12/07/98 Time: 8:23p -- Updated in $/MegaCore/HandOff/45/source/src -- ZMA- I checked this in on OT machine without figureing out what are the -- changes. -- -- ***************** Version 30 ***************** -- User: Nprasad Date: 12/03/98 Time: 6:16p -- Updated in $/MegaCore/HandOff/45/source/src -- -- ***************** Version 29 ***************** -- User: Nprasad Date: 11/30/98 Time: 5:53p -- Updated in $/MegaCore/HandOff/45/source/src -- Added some comments to all the files. I'M DONE!! I'M DONE!! -- -- ***************** Version 28 ***************** -- User: Nprasad Date: 11/30/98 Time: 3:36p -- Updated in $/MegaCore/HandOff/45/source/src -- Changed the Master Write State Machine and the relevant signals to the -- new specification. Ran simulations and fixed several bugs. -- -- ***************** Version 27 ***************** -- User: Nprasad Date: 11/29/98 Time: 4:24p -- Updated in $/MegaCore/HandOff/45/source/src -- Added capability to indicate a pure 64 bit system to. Parameter -- 64bit_system. -- -- ***************** Version 26 ***************** -- User: Nprasad Date: 11/29/98 Time: 3:51p -- Updated in $/MegaCore/HandOff/45/source/src -- Changed lm_ack, irdy, frame and req64 to meet the new specifications -- and logic. Also added lm_req32 as a control signal to trigger the -- master core to request the bus. -- -- ***************** Version 25 ***************** -- User: Nprasad Date: 11/29/98 Time: 2:31p -- Updated in $/MegaCore/HandOff/45/source/src -- Master Write State Machine is now changed to the new specification. It -- suports: -- 32 bit burst through lm_req32 -- 32 bit single cycle -- 32 bit io cycle -- 64 bit burst -- 64 bit single cycle <-- Only if the bus contains exclusively 64 bit -- devices -- -- ***************** Version 24 ***************** -- User: Nprasad Date: 11/25/98 Time: 4:56p -- Updated in $/MegaCore/HandOff/45/source/src -- Added some comments. -- -- ***************** Version 23 ***************** -- User: Otan Date: 11/25/98 Time: 1:33p -- Updated in $/MegaCore/HandOff/45/source/src -- Master Write Simulations Work. -- -- ***************** Version 22 ***************** -- User: Nprasad Date: 11/24/98 Time: 4:02p -- Updated in $/MegaCore/HandOff/45/source/src -- Checked the Master Write State Machine -- -- ***************** Version 21 ***************** -- User: Otan Date: 11/23/98 Time: 7:04p -- Updated in $/MegaCore/HandOff/45/source/src -- Master Write debugging 64-64 and 32-64. -- -- ***************** Version 20 ***************** -- User: Otan Date: 11/23/98 Time: 3:50p -- Updated in $/MegaCore/HandOff/45/source/src -- Target Read Simulations successful. Added 64-bit -> 64-bit and 32-bit -- -> 64-bit transactions. -- -- ***************** Version 19 ***************** -- User: Nprasad Date: 11/23/98 Time: 11:32a -- Updated in $/MegaCore/HandOff/45/source/src -- Fixed 32-->64 State Machine in Target. -- -- ***************** Version 18 ***************** -- User: Otan Date: 11/23/98 Time: 10:19a -- Updated in $/MegaCore/HandOff/45/source/src -- -- ***************** Version 17 ***************** -- User: Otan Date: 11/20/98 Time: 7:21p -- Updated in $/MegaCore/HandOff/45/source/src -- 64-bit Target Read Debugging -- -- ***************** Version 16 ***************** -- User: Otan Date: 11/20/98 Time: 4:20p -- Updated in $/MegaCore/HandOff/45/source/src -- 64-bit Target Write and Memory Read works with simulation, local and -- PCI wait states. -- Added l_ldata_ackn and l_hdata_ackn to distinguish low and high dwords -- for 32-bit PCI. -- -- ***************** Version 15 ***************** -- User: Otan Date: 11/19/98 Time: 1:55p -- Updated in $/MegaCore/HandOff/45/source/src -- 32-bit finished, except for data timeout. -- -- ***************** Version 14 ***************** -- User: Otan Date: 11/18/98 Time: 7:51p -- Updated in $/MegaCore/HandOff/45/source/src -- Master Read/Write works for single and burst cycles for PCI and local -- wait states. -- -- ***************** Version 13 ***************** -- User: Otan Date: 11/17/98 Time: 10:27p -- Updated in $/MegaCore/HandOff/45/source/src -- Master Read simulating successfully, except for lm_ackn -- -- ***************** Version 12 ***************** -- User: Nprasad Date: 11/17/98 Time: 8:33p -- Updated in $/MegaCore/HandOff/45/source/src -- Added 64 bit place holders for all of the files. Completed par gen and -- parity check for 64 bit. -- -- ***************** Version 11 ***************** -- User: Nprasad Date: 11/16/98 Time: 10:05p -- Updated in $/MegaCore/HandOff/45/source/src -- Changed Master Datapath to the top level. Added the extra signals -- needed. -- -- ***************** Version 10 ***************** -- User: Otan Date: 11/16/98 Time: 2:44p -- Updated in $/MegaCore/HandOff/45/source/src -- Target Read Hold Registers Implemented. -- Changed the ad_ce_nc=trg_ador_ena. -- Target Read/Write single and burst cycle simulations with local and PCI -- wait states successful. -- -- ***************** Version 9 ***************** -- User: Otan Date: 11/15/98 Time: 10:36p -- Updated in $/MegaCore/HandOff/45/source/src -- -- ***************** Version 8 ***************** -- User: Otan Date: 11/14/98 Time: 7:13p -- Updated in $/MegaCore/HandOff/45/source/src -- Working on Master Read -- -- ***************** Version 7 ***************** -- User: Otan Date: 11/14/98 Time: 1:13p -- Updated in $/MegaCore/HandOff/45/source/src -- Target Read Successfully Simulated with Local and PCI wait states. -- -- ***************** Version 6 ***************** -- User: Otan Date: 11/13/98 Time: 6:00p -- Updated in $/MegaCore/HandOff/45/source/src -- target read successfully simulated. -- -- ***************** Version 5 ***************** -- User: Nprasad Date: 11/12/98 Time: 11:49p -- Updated in $/MegaCore/HandOff/45/source/src -- Changed the output data path to the top level. Change the CE for the -- input Ad registers so that data and command are till the next cycle. -- Changed the Target local read state machine and the rest of the signals -- to adjust for the change in the datapath. First draft for target local -- read. Minor tweaks elsewhere. -- -- ***************** Version 4 ***************** -- User: Nprasad Date: 11/11/98 Time: 10:28p -- Updated in $/MegaCore/HandOff/45/source/src -- Target local write data path complete. Target local write state machine -- complete. Signals were modified to fucntion as specified. First draft. -- -- ***************** Version 3 ***************** -- User: Nprasad Date: 11/11/98 Time: 7:11p -- Updated in $/MegaCore/HandOff/45/source/src -- Address path has changed. Data path is through a partial change. -- New signal names added. Other superficial changes. -- -- ***************** Version 2 ***************** -- User: Nprasad Date: 10/26/98 Time: 11:42a -- Updated in $/MegaCore/HandOff/45/source/src -- Removed PCI_B Comments and Optmization -- -- ***************** Version 1 ***************** -- User: Ziada Date: 10/22/98 Time: 4:34p -- Created in $/MegaCore/HandOff/45/source/src -- -- ***************** Version 11 ***************** -- User: Ziada Date: 9/17/98 Time: 10:01a -- Updated in $/MegaCore/HandOff/40/source/src -- Changed Name of the perr_det_set to perr_set_detR -- SUBDESIGN 'pcic_pk' ( clk : INPUT; -- PCI clk Input rstn : INPUT; -- PCI rstn Input par : INPUT; -- PCI par signal trg_64_trans_out : INPUT; mstr_64_trans_out : INPUT; --jot trg_adr_phase_out : INPUT; --jot lm_adr_ackn : INPUT; low_ad_IR_addr[31..0] : INPUT; -- PCI AD Bus Input Registers low_cben_IR_addr[3..0] : INPUT; -- PCI CBEN Bus Input Registers low_ad_IR[31..0] : INPUT; -- PCI AD Bus Input Registers low_cben_IR[3..0] : INPUT; -- PCI CBEN Bus Input Registers par64 : INPUT; -- PCI par signal high_ad_IR[31..0] : INPUT; -- PCI AD Bus Input Registers high_cben_IR[3..0] : INPUT; -- PCI CBEN Bus Input Registers perr_ena : INPUT; -- Configuration Command Register Parity Enable serr_ena : INPUT; -- Configuration Command Register System Error Enable mstr_perr_vld : INPUT; -- Master Data Parity error valid targ_perr_vld : INPUT; -- Target Data Parity error Valid targ_serr_vld : INPUT; -- Target System Error valid perr_det_set : OUTPUT; -- PERR Detect Set, Config Status Register Bit 15 Set serr_sig_set : OUTPUT; -- System Error Signaled Set perr_out : OUTPUT; -- Parity Error Output serr_out : OUTPUT; -- System Error Output ) VARIABLE perr_det_setR_r1 : DFFE; -- Parity Error Detect Set SR15 Set perr_det_setR_r2 : DFFE; -- Parity Error Detect Set SR15 Set perr_det_setR_r3 : DFFE; -- Parity Error Detect Set SR15 Set perr_det_setR_r1_d : NODE; -- Parity Error Detect Set SR15 Set perr_det_setR_r2_d : NODE; -- Parity Error Detect Set SR15 Set perr_det_setR_r3_d : NODE; -- Parity Error Detect Set SR15 Set perr_det_setR : NODE; -- perr_rep_set : DFFE; -- Parity Error Report Set SR8 Set -- serr_sig_set : DFFE; -- System Error Signaled Set SR14 Set -- xor_chk : xor_36; -- Parity Checker XOR Tree xor_chk_out : NODE; -- Parity Checker XOR Tree Output xor_chk_out64 : NODE; -- Parity Checker XOR Tree Output xor_chk_outad : NODE; -- Parity Checker XOR Tree Output -- par_error_stat : NODE; -- Par error detected -- par_error_perr : NODE; -- Par error detected par_error_serr : NODE; -- Par error detected par_error : NODE; par_error64 : NODE; perr_OR : NODE; -- Perr Output Register perr_OR_not : DFFE; -- Perr Output Register perr_OR_not_lc1 : NODE; perr_OR_not_lc2 : NODE; perr_OR_not_lc3 : NODE; serr_OR : DFFE; -- Serr Output Register serr_or_lc : NODE; xxlad[11..0] : LCELL; -- Intermediate XOR Gates xxl[11..0] : LCELL; -- Intermediate XOR Gates xxh[11..0] : LCELL; -- Intermediate XOR Gates BEGIN -- Parity generation equations for the lower data xxlad0 = low_ad_IR_addr0 $ low_ad_IR_addr1 $ low_ad_IR_addr2 $ low_ad_IR_addr3; xxlad1 = low_ad_IR_addr4 $ low_ad_IR_addr5 $ low_ad_IR_addr6 $ low_ad_IR_addr7; xxlad2 = low_ad_IR_addr8 $ low_ad_IR_addr9 $ low_ad_IR_addr10 $ low_ad_IR_addr11; xxlad3 = low_ad_IR_addr12 $ low_ad_IR_addr13 $ low_ad_IR_addr14 $ low_ad_IR_addr15; xxlad4 = low_ad_IR_addr16 $ low_ad_IR_addr17 $ low_ad_IR_addr18 $ low_ad_IR_addr19; xxlad5 = low_ad_IR_addr20 $ low_ad_IR_addr21 $ low_ad_IR_addr22 $ low_ad_IR_addr23; xxlad6 = low_ad_IR_addr24 $ low_ad_IR_addr25 $ low_ad_IR_addr26 $ low_ad_IR_addr27; xxlad7 = low_ad_IR_addr28 $ low_ad_IR_addr29 $ low_ad_IR_addr30 $ low_ad_IR_addr31; xxlad8 = low_cben_IR_addr0 $ low_cben_IR_addr1 $ low_cben_IR_addr2 $ low_cben_IR_addr3; xxlad9 = xxlad0 $ xxlad1 $ xxlad2 $ xxlad3; xxlad10 = xxlad4 $ xxlad5 $ xxlad6 $ xxlad7; xxlad11 = xxlad8 $ xxlad9 $ xxlad10; xor_chk_outad = xxlad11 ; -- Parity generation equations for the lower data xxl0 = low_ad_IR0 $ low_ad_IR1 $ low_ad_IR2 $ low_ad_IR3; xxl1 = low_ad_IR4 $ low_ad_IR5 $ low_ad_IR6 $ low_ad_IR7; xxl2 = low_ad_IR8 $ low_ad_IR9 $ low_ad_IR10 $ low_ad_IR11; xxl3 = low_ad_IR12 $ low_ad_IR13 $ low_ad_IR14 $ low_ad_IR15; xxl4 = low_ad_IR16 $ low_ad_IR17 $ low_ad_IR18 $ low_ad_IR19; xxl5 = low_ad_IR20 $ low_ad_IR21 $ low_ad_IR22 $ low_ad_IR23; xxl6 = low_ad_IR24 $ low_ad_IR25 $ low_ad_IR26 $ low_ad_IR27; xxl7 = low_ad_IR28 $ low_ad_IR29 $ low_ad_IR30 $ low_ad_IR31; xxl8 = low_cbeN_IR0 $ low_cbeN_IR1 $ low_cbeN_IR2 $ low_cbeN_IR3; xxl9 = xxl0 $ xxl1 $ xxl2 $ xxl3; xxl10 = xxl4 $ xxl5 $ xxl6 $ xxl7; xxl11 = xxl8 $ xxl9 $ xxl10; xor_chk_out = xxl11 ; -- Parity generation equations for the upper data xxh0 = high_ad_IR0 $ high_ad_IR1 $ high_ad_IR2 $ high_ad_IR3; xxh1 = high_ad_IR4 $ high_ad_IR5 $ high_ad_IR6 $ high_ad_IR7; xxh2 = high_ad_IR8 $ high_ad_IR9 $ high_ad_IR10 $ high_ad_IR11; xxh3 = high_ad_IR12 $ high_ad_IR13 $ high_ad_IR14 $ high_ad_IR15; xxh4 = high_ad_IR16 $ high_ad_IR17 $ high_ad_IR18 $ high_ad_IR19; xxh5 = high_ad_IR20 $ high_ad_IR21 $ high_ad_IR22 $ high_ad_IR23; xxh6 = high_ad_IR24 $ high_ad_IR25 $ high_ad_IR26 $ high_ad_IR27; xxh7 = high_ad_IR28 $ high_ad_IR29 $ high_ad_IR30 $ high_ad_IR31; xxh8 = high_cbeN_IR0 $ high_cbeN_IR1 $ high_cbeN_IR2 $ high_cbeN_IR3; xxh9 = xxh0 $ xxh1 $ xxh2 $ xxh3; xxh10 = xxh4 $ xxh5 $ xxh6 $ xxh7; xxh11 = xxh8 $ xxh9 $ xxh10; xor_chk_out64 = xxh11 ; -- -- par error is detectd when output of xor tree and par are different -- -- You can avoid the CASCADE chain by replicating the logic and doing the AND gate implementation -- before the XOR ie with the output of xor_36. This is wherever par_error is used. -- --JOT par_error_stat = xor_chk_out xor par xor xor_chk_out64 xor par64; -- Par and xor tree output are differen --JOT par_error_perr = xor_chk_out xor par xor xor_chk_out64 xor par64; -- Par and xor tree output are differen --JOT par_error_serr = xor_chk_out xor par xor xor_chk_out64 xor par64; -- Par and xor tree output are differen par_error = (xor_chk_out xor par);-- and (not trg_adr_phase_out); --and lm_adr_ackn); par_error64 = (xor_chk_out64 xor par64); -- par_error_stat = (par_error or par_error64);-- and (not trg_adr_phase_out);-- and lm_adr_ackn); -- Par and xor tree output are differen -- par_error_perr = (par_error or par_error64);-- and (not trg_adr_phase_out);-- and lm_adr_ackn); -- Par and xor tree output are differen par_error_serr = (xor_chk_outad xor par);-- and (trg_adr_phase_out);-- or not lm_adr_ackn); -- or (xor_chk_out64 xor par64); -- Par and xor tree output are differen -- Parity error Output is set when either master or target detected a parity error -- and parity error reporting is enabled in the Config Command Register. -- perr_OR_not.clk = clk; -- perr_OR.clrn = rstn; perr_OR_not.prn = rstn; -- perr_OR = (par_error and (mstr_perr_vld or targ_perr_vld) and perr_ena) -- OR (par_error64 and ((mstr_perr_vld and mstr_64_trans_out) or (targ_perr_vld and trg_64_trans_out)) and perr_ena); -- perr_OR = (par_error and (mstr_perr_vld or targ_perr_vld) and perr_ena) -- OR (par_error64 and perr_ena and (mstr_perr_vld and mstr_64_trans_out) ) -- OR (par_error64 and perr_ena and (targ_perr_vld and trg_64_trans_out) ); perr_OR_not_lc1 = LCELL( (mstr_perr_vld or targ_perr_vld) and perr_ena); perr_OR_not_lc2 = LCELL(perr_ena and mstr_perr_vld and mstr_64_trans_out ); perr_OR_not_lc3 = LCELL(perr_ena and targ_perr_vld and trg_64_trans_out); perr_OR_not = not ( (par_error and perr_OR_not_lc1 ) ) and CASCADE ( not (par_error64 and ( perr_OR_not_lc2 OR perr_OR_not_lc3) ) ); -- perr_OR_not = not ( (par_error and (mstr_perr_vld or targ_perr_vld) and perr_ena) ) -- AND CASCADE ( (not( (par_error64 and perr_ena and mstr_perr_vld and mstr_64_trans_out ))) -- AND CASCADE ( not( (par_error64 and perr_ena and targ_perr_vld and trg_64_trans_out))) -- ); perr_OR = not perr_OR_not; perr_out = perr_OR; -- -- System error is asserted if a target address phase detected a parity error and -- both perr reporting and serr reporting are set -- serr_OR.clk = clk; serr_OR.clrn = rstn; -- serr_OR = LCELL (targ_serr_vld and serr_ena and perr_ena) and par_error_serr; serr_or_lc = LCELL(targ_serr_vld and serr_ena and perr_ena); serr_OR = serr_or_lc and par_error_serr; serr_out = serr_OR; -- -- serr_sig_set: This is set whenever the target asserts serr. -- serr_sig_set = serr_OR; -- -- perr_det_setR is a register to remove par from the path. -- perr det bit in status regsiter must be set when a parity error is detected even -- if the parity error reporting is not enabled in the command register -- ---------- CASCADE OPTIMIZATION ------------------------------------------------------------- % perr_det_setR_not.clk = clk; -- perr_det_setR.clrn = rstn; perr_det_setR_not.prn = rstn; -- perr_det_setR = (mstr_perr_vld OR targ_perr_vld OR targ_serr_vld) and par_error; -- perr_det_setR = ((((trg_64_trans_out and targ_perr_vld) or (mstr_64_trans_out and mstr_perr_vld) or targ_serr_vld)) and par_error_stat) -- OR -- ((((not trg_64_trans_out and targ_perr_vld) or (not mstr_64_trans_out and mstr_perr_vld) or targ_serr_vld)) and (par_error or par_error_serr)) -- ; -- perr_det_setR = (par_error and (mstr_perr_vld or targ_perr_vld)) -- OR (par_error64 and ((mstr_perr_vld and mstr_64_trans_out) or (targ_perr_vld and trg_64_trans_out))) -- OR (targ_serr_vld and par_error_serr); perr_det_setR_not = not (par_error64 and LCELL ( (mstr_perr_vld and mstr_64_trans_out) or (targ_perr_vld and trg_64_trans_out) ) ) and CASCADE ( (not (par_error and (mstr_perr_vld or targ_perr_vld) ) ) and CASCADE ( not (targ_serr_vld and par_error_serr) ) ); perr_det_setR = not perr_det_setR_not; perr_det_set = perr_det_setR; % ------------------------------------------------------------------------------------------------ -------------- REGISTER-OR OPTIMIZATION ----------------------------------------------------- -- perr_det_setR.clk = clk; -- perr_det_setR.clrn = rstn; -- perr_det_setR_not.prn = rstn; -- perr_det_setR = (mstr_perr_vld OR targ_perr_vld OR targ_serr_vld) and par_error; -- perr_det_setR = ((((trg_64_trans_out and targ_perr_vld) or (mstr_64_trans_out and mstr_perr_vld) or targ_serr_vld)) and par_error_stat) -- OR -- ((((not trg_64_trans_out and targ_perr_vld) or (not mstr_64_trans_out and mstr_perr_vld) or targ_serr_vld)) and (par_error or par_error_serr)) -- ; -- perr_det_setR = (par_error and (mstr_perr_vld or targ_perr_vld)) -- OR (par_error64 and ((mstr_perr_vld and mstr_64_trans_out) or (targ_perr_vld and trg_64_trans_out))) -- OR (targ_serr_vld and par_error_serr); -- perr_det_setR_not = not (par_error64 and LCELL ( (mstr_perr_vld and mstr_64_trans_out) or (targ_perr_vld and trg_64_trans_out) ) ) -- and CASCADE ( (not (par_error and (mstr_perr_vld or targ_perr_vld) ) ) -- and CASCADE ( not (targ_serr_vld and par_error_serr) ) -- ); perr_det_setR_r1.clk = clk; perr_det_setR_r1.clrn = rstn; perr_det_setR_r1_d = (par_error and (mstr_perr_vld or targ_perr_vld)); perr_det_setR_r1.d = perr_det_setR_r1_d; perr_det_setR_r2.clk = clk; perr_det_setR_r2.clrn = rstn; perr_det_setR_r2_d = (par_error64 and LCELL((mstr_perr_vld and mstr_64_trans_out) or (targ_perr_vld and trg_64_trans_out))); perr_det_setR_r2.d = perr_det_setR_r2_d; perr_det_setR_r3.clk = clk; perr_det_setR_r3.clrn = rstn; perr_det_setR_r3_d = (targ_serr_vld and par_error_serr); perr_det_setR_r3.d = perr_det_setR_r3_d; perr_det_setR = perr_det_setR_r1 or perr_det_setR_r2 or perr_det_setR_r3; perr_det_set = perr_det_setR; % Ziad's optimization -- -- Parity error Output is set when either master or target detected a parity error -- and parity error reporting is enabled in the Config Command Register. -- perr_OR.clk = clk; perr_OR.clrn = rstn; perr_OR = cascade ( (mstr_perr_vld or targ_perr_vld) and perr_ena) and par_error_perr; perr_out = perr_OR; -- -- System error is asserted if a target address phase detected a parity error and -- both perr reporting and serr reporting are set -- serr_OR.clk = clk; serr_OR.clrn = rstn; serr_OR = cascade (targ_serr_vld and serr_ena and perr_ena) and (par_error_serr); serr_out = serr_OR; -- -- serr_sig_set: This is set whenever the target asserts serr. -- serr_sig_set = serr_OR; -- -- perr_det_setR is a register to remove par from the path. -- perr det bit in status regsiter must be set when a parity error is detected even -- if the parity error reporting is not enabled in the command register -- perr_det_setR.clk = clk; perr_det_setR.clrn = rstn; perr_det_setR = cascade (mstr_perr_vld OR targ_perr_vld OR targ_serr_vld) and par_error_stat; perr_det_set = perr_det_setR; % END;