www.pudn.com > pci_core.rar > pci_c.tdf
-- File Name : pci_c.tdf
-- Date Created : 11/09/1998
-- Designer Name : Nitin Parsad, Oliver Tan, Ziad Abu-Lebdeh
-- Company Name : Altera Corporation
-- Company Address: 101 Innovation Drive
-- San Jose, California 95134
-- U.S.A.
--
--
-- Copyright Altera Corporation 1998
--
--
-- This is the Top Level Design for PCI/C MegaCore
-- This MegaCore supports The following
-- - 64 Bit Master/Target Interface
-- - 64 Bit Target Only Interface
-- - 32 Bit Master/Target Interface
-- - 32 Bit Target Only Interface
--
-- The following are the naming conventions used.
-- The following are the signal name endings with x being a signal name
--
-- x : active high signal
-- xi : Active High Input signal
-- xo : Active high Output Signal
-- xn : Active Low Signal
-- xni : Active Low Input Signal
-- xno : Active Low Output Signal
-- xr : Active High registered Signal
-- xir : Active High registered Input signal
-- xnir: Active Low registered Input signal
-- xor : Active High registered output signal
-- xnor: Active Low registered Output signal
--
--
-- $History: pci_c.tdf $
--
-- ***************** Version 115 *****************
-- User: Afauria Date: 6/17/99 Time: 12:54p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 114 *****************
-- User: Afauria Date: 6/17/99 Time: 12:21p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 113 *****************
-- User: Afauria Date: 6/17/99 Time: 12:20p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 111 *****************
-- User: Otan Date: 6/17/99 Time: 12:42a
-- Updated in $/MegaCore/HandOff/45/source/src
-- ver1.1
--
-- ***************** Version 110 *****************
-- User: Afauria Date: 6/17/99 Time: 12:13a
-- Updated in $/MegaCore/HandOff/45/source/src
-- 130E ce
--
-- ***************** Version 109 *****************
-- User: Otan Date: 6/16/99 Time: 9:40p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 50e ad_ce
--
-- ***************** Version 108 *****************
-- User: Otan Date: 6/16/99 Time: 4:10p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Fixed 32-bit, 64-bit local target read
--
-- ***************** Version 106 *****************
-- User: Otan Date: 6/14/99 Time: 1:15p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Optimized frame_or and req64_or for setup
--
-- ***************** Version 105 *****************
-- User: Otan Date: 6/12/99 Time: 12:44p
-- Updated in $/MegaCore/HandOff/45/source/src
-- optimized ir_ce_a.
--
-- ***************** Version 104 *****************
-- User: Otan Date: 6/11/99 Time: 7:21p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Optimized hr_dat_sel
--
-- ***************** Version 103 *****************
-- User: Otan Date: 6/11/99 Time: 4:15p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Optimized stop, lt_ack, hi_low_sel.
--
-- ***************** Version 102 *****************
-- User: Otan Date: 6/11/99 Time: 11:26a
-- Updated in $/MegaCore/HandOff/45/source/src
-- More optimization. targ_oer, high_ad_or, bar_hit[5..0]
--
-- ***************** Version 101 *****************
-- User: Otan Date: 6/10/99 Time: 1:34p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 100 *****************
-- User: Otan Date: 6/09/99 Time: 9:10p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 99 *****************
-- User: Otan Date: 6/09/99 Time: 6:41p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 98 *****************
-- User: Otan Date: 6/09/99 Time: 3:20p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Optimized master and top-level tdf
--
-- ***************** Version 97 *****************
-- User: Otan Date: 6/09/99 Time: 12:22p
-- Updated in $/MegaCore/HandOff/45/source/src
-- added target_device support
--
-- ***************** Version 96 *****************
-- User: Otan Date: 6/09/99 Time: 9:47a
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 95 *****************
-- User: Otan Date: 6/09/99 Time: 9:31a
-- Updated in $/MegaCore/HandOff/45/source/src
-- vers1.1 - more optimizing, ready to make acfs
--
-- ***************** Version 94 *****************
-- User: Otan Date: 6/09/99 Time: 9:19a
-- Updated in $/MegaCore/HandOff/45/source/src
-- all features added - only 8 LSB of BAR1 are read/write in a 64-bit BAR
--
-- ***************** Version 93 *****************
-- User: Otan Date: 6/07/99 Time: 7:43p
-- Updated in $/MegaCore/HandOff/45/source/src
-- DAC fixes - non-aligned QWORD transactions
--
-- ***************** Version 92 *****************
-- User: Otan Date: 6/07/99 Time: 11:33a
-- Updated in $/MegaCore/HandOff/45/source/src
-- 6/7/99 - Optimized DAC works. Need to check non-aligned QWORD target
-- read
--
-- ***************** Version 91 *****************
-- User: Otan Date: 6/04/99 Time: 6:42p
-- Updated in $/MegaCore/HandOff/45/source/src
-- dac optimization
--
-- ***************** Version 90 *****************
-- User: Otan Date: 5/22/99 Time: 8:33a
-- Updated in $/MegaCore/HandOff/45/source/src
-- 5/22/99
--
-- ***************** Version 89 *****************
-- User: Otan Date: 5/15/99 Time: 1:57p
-- Updated in $/MegaCore/HandOff/45/source/src
-- DAC - master and target simulations work
--
-- ***************** Version 86 *****************
-- User: Otan Date: 4/22/99 Time: 2:35p
-- Updated in $/MegaCore/HandOff/45/source/src
-- DAC - master simulations work
--
-- ***************** Version 85 *****************
-- User: Otan Date: 4/19/99 Time: 9:36a
-- Updated in $/MegaCore/HandOff/45/source/src
-- DAC - master mode operation works (master read and master write)
--
-- ***************** Version 84 *****************
-- User: Otan Date: 4/15/99 Time: 9:50a
-- Updated in $/MegaCore/HandOff/45/source/src
-- pre1.1 - DAC - master mode - simulates for burs read/write and
-- single-cycle read.
--
-- ***************** Version 83 *****************
-- User: Otan Date: 4/14/99 Time: 1:17p
-- Updated in $/MegaCore/HandOff/45/source/src
-- rev1a on dac
--
-- ***************** Version 82 *****************
-- User: Otan Date: 4/08/99 Time: 1:49p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 79 *****************
-- User: Otan Date: 4/06/99 Time: 8:27a
-- Updated in $/MegaCore/HandOff/45/source/src
-- edited lt_framen and lm_req64r
--
-- ***************** Version 78 *****************
-- User: Otan Date: 3/16/99 Time: 3:07p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 77 *****************
-- User: Otan Date: 3/16/99 Time: 12:14p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added default parameter settings
--
-- ***************** Version 76 *****************
-- User: Ziada Date: 3/15/99 Time: 5:40p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added New parameter PCI_66MHZ_CAPABLE
--
-- ***************** Version 75 *****************
-- User: Otan Date: 3/14/99 Time: 2:15p
-- Updated in $/MegaCore/HandOff/45/source/src
-- pre1.0-4
--
-- ***************** Version 74 *****************
-- User: Otan Date: 3/14/99 Time: 8:54a
-- Updated in $/MegaCore/HandOff/45/source/src
-- pre1.0-2
--
-- ***************** Version 73 *****************
-- User: Otan Date: 3/11/99 Time: 9:26a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Read with 1 word in pipe, followed by target write. Should do a
-- retry.
--
-- Single cycle fast back to back.
--
-- ***************** Version 72 *****************
-- User: Afauria Date: 3/10/99 Time: 12:18p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 71 *****************
-- User: Otan Date: 3/09/99 Time: 3:29p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 70 *****************
-- User: Afauria Date: 3/09/99 Time: 1:00p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 68 *****************
-- User: Afauria Date: 3/09/99 Time: 12:39p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Optimizing for 66MHz
--
-- ***************** Version 67 *****************
-- User: Otan Date: 3/08/99 Time: 11:17a
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 66 *****************
-- User: Otan Date: 3/05/99 Time: 11:16a
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 65 *****************
-- User: Otan Date: 3/05/99 Time: 10:57a
-- Updated in $/MegaCore/HandOff/45/source/src
-- 66 MHz Optimized
--
-- ***************** Version 63 *****************
-- User: Otan Date: 3/03/99 Time: 2:47p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 66 mhz optimization. Need to look at double cascade on irdy_or_not and
-- trdy_or_not.
--
-- ***************** Version 62 *****************
-- User: Otan Date: 3/02/99 Time: 2:23p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 66 MHz Optimization
--
-- ***************** Version 61 *****************
-- User: Otan Date: 3/02/99 Time: 10:24a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Simulations work
--
-- ***************** Version 60 *****************
-- User: Otan Date: 2/26/99 Time: 6:05p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Fixed fast_back-to-back
--
-- ***************** Version 59 *****************
-- User: Otan Date: 2/26/99 Time: 11:53a
-- Updated in $/MegaCore/HandOff/45/source/src
-- MS_REQ Optimization fixed
--
-- ***************** Version 57 *****************
-- User: Otan Date: 2/17/99 Time: 5:12p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 56 *****************
-- User: Otan Date: 2/16/99 Time: 7:56p
-- Updated in $/MegaCore/HandOff/45/source/src
-- master write simulations
--
-- ***************** Version 55 *****************
-- User: Otan Date: 2/09/99 Time: 8:58a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Updated for Master Read simulations. 2/9/99
--
-- ***************** Version 54 *****************
-- User: Otan Date: 2/05/99 Time: 11:11a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Fixed master abort
--
-- ***************** Version 53 *****************
-- User: Otan Date: 2/02/99 Time: 4:14p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Fixed system parity error
--
-- ***************** Version 52 *****************
-- User: Otan Date: 2/02/99 Time: 2:11p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 51 *****************
-- User: Otan Date: 2/02/99 Time: 1:07p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Updated master parity error
--
-- ***************** Version 50 *****************
-- User: Otan Date: 1/29/99 Time: 11:59a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Been Optimized to meet 33MHz performance.
--
-- ***************** Version 49 *****************
-- User: Otan Date: 1/28/99 Time: 8:31a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master and Target Optimizations. These files are before we changed
-- ador_hi_dena in pcic_t.tdf.
--
-- ***************** Version 48 *****************
-- User: Otan Date: 1/27/99 Time: 9:07a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target and Master Optimizations
--
-- ***************** Version 47 *****************
-- User: Otan Date: 1/25/99 Time: 10:43a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target Optimization
--
-- ***************** Version 46 *****************
-- User: Otan Date: 1/21/99 Time: 4:26p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target Write and Read have been extensively simulated
--
-- ***************** Version 45 *****************
-- User: Otan Date: 12/24/98 Time: 12:49p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 44 *****************
-- User: Otan Date: 12/22/98 Time: 4:26p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Fixing wait states for each data phase
--
-- ***************** Version 43 *****************
-- User: Otan Date: 12/16/98 Time: 7:33a
-- Updated in $/MegaCore/HandOff/45/source/src
-- for beta release
--
-- ***************** Version 41 *****************
-- User: Otan Date: 12/16/98 Time: 7:00a
-- Updated in $/MegaCore/HandOff/45/source/src
-- for beta release
--
-- ***************** Version 39 *****************
-- User: Otan Date: 12/15/98 Time: 9:28p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 38 *****************
-- User: Otan Date: 12/14/98 Time: 11:17p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 35 *****************
-- User: Otan Date: 12/10/98 Time: 8:09p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Ziad checked it in without figuring out what changed
--
-- ***************** Version 34 *****************
-- User: Ziada Date: 12/09/98 Time: 4:23p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 33 *****************
-- User: Otan Date: 12/08/98 Time: 4:59p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 32 *****************
-- User: Ziada Date: 12/08/98 Time: 11:40a
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 31 *****************
-- User: Otan Date: 12/04/98 Time: 10:23a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Latest signal names
--
-- ***************** Version 30 *****************
-- User: Nprasad Date: 11/30/98 Time: 5:53p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added some comments to all the files. I'M DONE!! I'M DONE!!
--
-- ***************** Version 29 *****************
-- User: Nprasad Date: 11/30/98 Time: 3:34p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Changed the Master Write State Machine and the relevant signals to the
-- new specification. Ran simulations and fixed several bugs.
--
-- ***************** Version 28 *****************
-- User: Nprasad Date: 11/29/98 Time: 4:23p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added capability to indicate a pure 64 bit system to. Parameter
-- 64bit_system.
--
-- ***************** Version 27 *****************
-- User: Nprasad Date: 11/29/98 Time: 3:51p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Changed lm_ack, irdy, frame and req64 to meet the new specifications
-- and logic. Also added lm_req32 as a control signal to trigger the
-- master core to request the bus.
--
-- ***************** Version 26 *****************
-- User: Nprasad Date: 11/29/98 Time: 2:31p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Write State Machine is now changed to the new specification. It
-- suports:
-- 32 bit burst through lm_req32
-- 32 bit single cycle
-- 32 bit io cycle
-- 64 bit burst
-- 64 bit single cycle <-- Only if the bus contains exclusively 64 bit
-- devices
--
-- ***************** Version 25 *****************
-- User: Nprasad Date: 11/25/98 Time: 4:56p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added some comments.
--
-- ***************** Version 24 *****************
-- User: Otan Date: 11/25/98 Time: 1:33p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Write Simulations Work.
--
-- ***************** Version 22 *****************
-- User: Otan Date: 11/23/98 Time: 7:04p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Write debugging 64-64 and 32-64.
--
-- ***************** Version 21 *****************
-- User: Otan Date: 11/23/98 Time: 3:37p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target Read Simulations successful. Added 64-bit -> 64-bit and 32-bit
-- -> 64-bit transactions.
--
-- ***************** Version 20 *****************
-- User: Nprasad Date: 11/23/98 Time: 11:32a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Fixed 32-->64 State Machine in Target.
--
-- ***************** Version 19 *****************
-- User: Otan Date: 11/20/98 Time: 7:24p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 18 *****************
-- User: Otan Date: 11/20/98 Time: 7:21p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 64-bit Target Read Debugging
--
-- ***************** Version 17 *****************
-- User: Otan Date: 11/20/98 Time: 4:20p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 64-bit Target Write and Memory Read works with simulation, local and
-- PCI wait states.
-- Added l_ldata_ackn and l_hdata_ackn to distinguish low and high dwords
-- for 32-bit PCI.
--
-- ***************** Version 16 *****************
-- User: Otan Date: 11/19/98 Time: 1:55p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 32-bit finished, except for data timeout.
--
-- ***************** Version 15 *****************
-- User: Otan Date: 11/18/98 Time: 7:51p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Read/Write works for single and burst cycles for PCI and local
-- wait states.
--
-- ***************** Version 14 *****************
-- User: Otan Date: 11/17/98 Time: 10:27p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Read simulating successfully, except for lm_ackn
--
-- ***************** Version 13 *****************
-- User: Nprasad Date: 11/17/98 Time: 8:33p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added 64 bit place holders for all of the files. Completed par gen and
-- parity check for 64 bit.
--
-- ***************** Version 12 *****************
-- User: Nprasad Date: 11/16/98 Time: 10:05p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Changed Master Datapath to the top level. Added the extra signals
-- needed.
--
-- ***************** Version 11 *****************
-- User: Otan Date: 11/16/98 Time: 2:55p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 6 *****************
-- User: Nprasad Date: 11/12/98 Time: 11:49p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Changed the output data path to the top level. Change the CE for the
-- input Ad registers so that data and command are till the next cycle.
-- Changed the Target local read state machine and the rest of the signals
-- to adjust for the change in the datapath. First draft for target local
-- ren. Minor tweaks elsewhere.
--
-- ***************** Version 5 *****************
-- User: Nprasad Date: 11/11/98 Time: 10:28p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target local write data path complete. Target local write state machine
-- complete. Signals were modified to fucntion as specified. First draft.
--
-- ***************** Version 4 *****************
-- User: Nprasad Date: 11/11/98 Time: 7:10p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Address path has changed. Data path is through a partial change.
-- New signal names added. Other superficial changes.
--
-- ***************** Version 3 *****************
-- User: Nprasad Date: 10/26/98 Time: 11:42a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Removed PCI_B Comments and Optmization
--
-- ***************** Version 2 *****************
-- User: Nprasad Date: 10/22/98 Time: 4:42p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Cleaned all history messages
--
--
-- ***************** Version 41 *****************
-- User: Otan Date: 10/21/98 Time: 9:41a
-- Updated in $/MegaCore/HandOff/35/source/src
-- ver3.02
--
FUNCTION pcic_m (clk, rstn, gnt, frame, irdy, trdy, devsel, stop, perr, mstr_ena, lat_dat[7..0],
lm_req64, lm_req32, lm_last, lm_rdyn, low_lm_dati[31..0], %lm_adri[31..0],% low_lm_beni[3..0], ack64, high_lm_dati[31..0],
high_lm_beni[3..0] %lm_cmd[3..0], 64bit_PCI%)--, lm_adr64)
WITH (OPTIMIZE_MSTR)
RETURNS (low_data_out[31..0], high_data_out[31..0], ad_oe, ad_sel, ad_ir_ce_D, cbe_ce, low_cbe_out[3..0], high_cbe_out[3..0], cbe_oe,
frame_out, frame_oe, irdy_out, irdy_oe, req_out, perr_vld, perr_oe, par_oe, perr_rep_set, targ_abrt_set, mstr_abrt_set,
lm_adr_ack, lm_ackn, %trdyrn,% lm_tsr[9..0], mstr_actv, hr_dat_sel, dati_HR_ena, ADOR_ena, hr_cbe_sel, cbe_HR_ena,
req64_out, req64_oe, hr_adr_sel, lm_ldata_ackn, lm_hdata_ackn, lm_dxfrn, ADOR_HI_DENA, HI_LOW_SEL, 64_trans_out, ad_ir_ce_a, cben_ir_ce_a,
cben_ir_ce_d, dac_decode_out);
FUNCTION pcic_pk (clk, rstn, par, low_ad_ir_addr[31..0], low_cben_ir_addr[3..0], low_ad_ir[31..0], low_cben_ir[3..0], par64, high_ad_ir[31..0], high_cben_ir[3..0], perr_ena,
serr_ena, mstr_perr_vld, targ_perr_vld, targ_serr_vld, trg_64_trans_out, mstr_64_trans_out%, trg_adr_phase_out, lm_adr_ackn%)
RETURNS (perr_det_set, serr_sig_set, perr_out, serr_out);
FUNCTION pcic_pg (data[31..0], cben[3..0])
RETURNS (parity);
FUNCTION pcic_t (clk, rstn, ad_ir_address[31..0], cben_ir_address[3..0], frame, irdy, idsel, low_lt_dati[31..0], lt_rdyn,
lt_discn, lt_abortn, perr_rep_set, perr_det_set, serr_sig_set, mstr_actv, mstr_abrt_set, targ_abrt_set,
lcfg_adr[7..0], lcfg_ben[3..0], lcfg_dat_in[31..0], lcfg_adr_vld, lcfg_dat_vld, lcfg_wr_rdn, req64, high_lt_dati[31..0],
%64bit_PCI,% lm_ackn, mstr_dac_decode, ad_ir_data[31..0], cben_ir_data[3..0])
WITH (Host_BRIDGE_ENA, OPTIMIZE_TARG, OPTIMIZE_ACK, DATA_TIMEOUT)
RETURNS (serr_vld, perr_vld, perr_oe, par_oe, lt_adr[63..0], lt_cmd[3..0], low_lt_ben[3..0], lt_framen,
lt_ackn, %irdyrn,% ad_oe, ad_sel, targ_oer, trdy_out, devsel_out, stop_out, high_lt_ben[3..0],
io_ena, mem_ena, mstr_ena, mwi_ena, perr_ena, serr_ena, cfg_perr_rep, cfg_tabrt_sig, cfg_tabrt_rcvd,
cfg_mabrt_rcvd, cfg_serr_sig, cfg_perr_det, lat_dat[7..0], cache_dat[7..0], %base_hit[5..0],% lt_tsr[11..0],
lt_dxfrn, lcfg_dat_out[31..0], ADOR_ena, ad_IR_ce_A, ad_IR_ce_D, cben_IR_ce_A, cben_IR_ce_D,
low_data_out[31..0], high_data_out[31..0], cfg_dat_out[31..0], cfg_cyc_out, hr_dat_sel, dati_HR_ena, ack64_out,
lt_ldata_ackn, lt_hdata_ackn, lt_sel_w, ador_hi_dena, hi_low_sel, 64_trans_out, adr_phase_out, dac_sr_out%, lt_lackn, lt_hackn%);
INCLUDE "maxplus2.inc";
PARAMETERS
(
TARGET_DEVICE = "EPF10K50EFC484",
PCI_66MHZ_CAPABLE = "YES",
HOST_BRIDGE_ENA = "NO", -- Enable Host Bridge Support
INTERNAL_ARBITER = "NO", -- Determines if REQ signal should have a tristate buffer or not.
VENDOR_ID = H"1172", -- Vendor ID Register
DEVICE_ID = H"0004", -- Device ID Register
REVISION_ID = H"01", -- Revision ID Register
CLASS_CODE = H"FF0000", -- Class Code Register
SUBSYSTEM_ID = H"0000", -- Subsystem ID Register
SUBSYSTEM_VENDOR_ID = H"0000", -- Subsystem Vendor ID Register
MIN_GRANT = H"00", -- Minimum Grant Register
MAX_LATENCY = H"00", -- Maximum Latency Register
CAP_LIST_ENA = "NO", -- Capabilities List
CAP_PTR = H"40",
EXP_ROM_ENA = "NO",
EXP_ROM_BAR = H"FFF00000", -- EXpansion ROM Base Address Register
USE_EXP_ROM_DEFAULT = "NO", -- Use The Expansion ROM BAR
EXP_ROM_DEFAULT = H"FFF00000", -- Expansion ROM Power Up Value
NUMBER_OF_BARS = 1, -- Number of Base Address Regisers to be used
BAR0 = H"FFF00000", -- Values in CFG_BAR0
BAR1 = H"FFF00000", -- Bit(0) = 0-Memory, 1-I/O Space
BAR2 = H"FFF00000", -- Bit(1) = Reserve for I/O Space
BAR3 = H"FFF00000", -- Bit(2,1) = Memory Type
BAR4 = H"FFF00000", -- Bit(3) = Prefetchable Memory Address
BAR5 = H"FFF00000", -- Bits(31..n) = 1 for number of decode bits
DUAL_ADDRESS_ENA = "YES",
64BIT_SYSTEM = "NO", -- Indicates whether this is a pure 64bit system or not
LOCAL_CONFIG_ENA = "NO", -- Enable Host Bridge Support
CORE = "MASTER", -- Type of Core interface used
DATA_TIMEOUT = 16 -- Load value for time counter on target
);
CONSTANT REVISION="VER 1.1 $Revision: 115 $, $JustDate: 6/17/99 $";
SUBDESIGN 'pci_c'
(
-- PCI Input Signals
clk : INPUT; -- PCI Clock
rstn : INPUT; -- PCI Reset
gntn : INPUT; -- PCI Grant
idsel : INPUT; -- PCI ID Select
-- PCI Output Signals
intan : OUTPUT; -- PCI Interrupt A
reqn : OUTPUT; -- PCI Request
serrn : OUTPUT; -- PCI System Error
-- PCI Bidir Signals
ad[63..0] : BIDIR; -- PCI Address/Data Bus
cben[7..0] : BIDIR; -- PCI Command/Byte Enables
par : BIDIR; -- PCI Parity
par64 : BIDIR; -- PCI Parity for Upper 32 bits
perrn : BIDIR; -- PCI Data Parity Error
-- framen : BIDIR; -- PCI Frame Signal
-- req64n : BIDIR; -- PCI 64 bit request
-- irdyn : BIDIR; -- PCI Initiator Ready
-- trdyn : BIDIR; -- PCI Target Ready
-- devseln : BIDIR; -- PCI Device Select
-- ack64n : BIDIR; -- PCI 64 acknowledge signal
-- stopn : BIDIR; -- PCI Transaction Stop
framen_in : INPUT; -- PCI Frame Signal INPUT
req64n_in : INPUT; -- PCI 64 bit request
irdyn_in : INPUT; -- PCI Initiator Ready INPUT
trdyn_in : INPUT; -- PCI Target Ready INPUT
devseln_in : INPUT; -- PCI Device Select
ack64n_in : INPUT; -- PCI 64 acknowledge signal
stopn_in : INPUT; -- PCI Transaction Stop
framen_out : OUTPUT; -- PCI Frame Signal OUTPUT
req64n_out : OUTPUT; -- PCI 64 bit request
irdyn_out : OUTPUT; -- PCI Initiator Ready OUTPUT
trdyn_out : OUTPUT; -- PCI Target Ready OUTPUT
devseln_out : OUTPUT; -- PCI Device Select
ack64n_out : OUTPUT; -- PCI 64 acknowledge signal
stopn_out : OUTPUT; -- PCI Transaction Stop
-- Local Address, Data, Command and Byte Enables
--IF (DUAL_ADDRESS_ENA == "NO" ) GENERATE
-- l_dati[63..0] : INPUT; -- Target Data Input
-- l_adri[31..0] : INPUT; -- Local Side Master Address/Data Bus
-- l_cmdi[3..0] : INPUT; -- Local Command
-- l_beni[7..0] : INPUT; -- Local Byte Enables
--ELSE GENERATE
l_adi[63..0] : INPUT; -- Local Side Address/Data Bus version 1.1
l_cbeni[7..0] : INPUT; -- Local Side Command/Byte Enable Bus version 1.1
--ELSE GENERATE;
l_adro[63..0] : OUTPUT; -- Target Address Output
l_dato[63..0] : OUTPUT; -- Target Data Output
l_beno[7..0] : OUTPUT; -- Target Byte Enable
l_cmdo[3..0] : OUTPUT; -- Target command
-- General Purpose Outputs
l_ldat_ackn : OUTPUT; -- Low Data Acknowledge
l_hdat_ackn : OUTPUT; -- High Data Acknowledge
-- Local Master Input Signals
-- lm_adr64n : INPUT = VCC; -- Local Master 64 Bit Address Request
lm_req32n : INPUT; -- Local Master 32-bit Request Transaction
lm_req64n : INPUT; -- Local Master 64-bit Request Transaction
lm_lastn : INPUT; -- Local Master End Transaction
lm_rdyn : INPUT; -- Local Master ready
-- Will assert waits on the next clock cycle
-- Local Master Output Signals
lm_adr_ackn : OUTPUT; -- Local Master Address Acknowledge
lm_ackn : OUTPUT; -- Master Transfer Acknowledge
-- When Asserted Indicates that Data is valid or Ready to recieve data
lm_dxfrn : OUTPUT;
lm_tsr[9..0] : OUTPUT; -- Master Transaction Status Registers
-- 0: Master is requesting the Bus
-- 1: Master has been Granted the bus
-- 2: Master is in Address Phase
-- 3: Master is Transferring data
-- 4: Latency Timer has expired
-- 5: Master Recieved a retry
-- 6: Master Recieved a Disconnect with 0 Data Transfers
-- 7: Master Recieved a Disconnect with 1 Data Transfers
-- 8: PCI data Xfr in Last Clock
-- 9: 64 bit transaction
-- Local Target Input Signals
lt_rdyn : INPUT; -- Local Target Ready
lt_abortn : INPUT; -- Instructs the Target to abort the current Transaction
lt_discn : INPUT; -- Instructs the Target to end the current Transaction with a Disconnect
-- or retry depending on the time when it was asserted
lirqn : INPUT; -- Local Interrupt Request
-- Local Target Output Signals
lt_framen : OUTPUT; -- Local Target Begin/End Transaction
lt_ackn : OUTPUT; -- Target Transfer Acknowledge
lt_dxfrn : OUTPUT; -- Target data transfer is occurring
lt_tsr[11..0] : OUTPUT; -- Target Transaction Status Registers
-- 5..0: Target Base Address Register accessed
-- 6: Target indicates an Expansion ROM hit
-- 7: Target transaction is 64 bit
-- 8: Target is accessed from PCI bus
-- lt_lackn : OUTPUT; -- Low Target Data Transfer Acknowledge
-- lt_hackn : OUTPUT; -- High Targer Data Transfer Acknowledge
-- Local Configuration Space Outputs
cmd_reg[5..0] : OUTPUT; -- PCI Configuration Command Registers Outputs
-- 0: I/O Enable ( Command Register Bit 0)
-- 1: Memory Enable ( Command Register Bit 1)
-- 2: Master Enable ( Command Register Bit 2)
-- 3: MWI Enable ( Command Register Bit 4)
-- 4: PERR Response Ena ( Command Register Bit 6)
-- 5: SERR Enable ( Command Register Bit 8)
-- Local Status Register Outputs
stat_reg[5..0] : OUTPUT; -- Status Register Outputs
-- 0: Data Parity Error Reported ( Status Register Bit 8)
-- 1: Signaled Target Abort ( Status Register Bit 11)
-- 2: Recieved Target Abort ( Status Register Bit 12)
-- 3: Recieved Master Abort ( Status Register Bit 13)
-- 4: Signaled System Error ( Status Register Bit 14)
-- 5: Detected Parit Error ( Status Register Bit 15)
-- Other Local Configuration Register Outputs
cache[7..0] : OUTPUT; -- Cache Line Register Data
)
VARIABLE
parity_Chk : pcic_pk; -- Parity Generator XOR Tree
parity_gen : pcic_pg; -- Parity Generator XOR Tree
parity_gen64 : pcic_pg; -- Parity Generator XOR Tree
trg : pcic_t; -- Instantiate Target Control Module
mstr : pcic_m; -- Instantiate Master Control Module
-- Internal Active High Input Nodes for PCI Signals
gnt : NODE; -- gnt Input
frame : NODE; -- Frame Input
irdy : NODE; -- Irdy Input
devsel : NODE; -- DEVSEL Input
trdy : NODE; -- trdy Input
stop : NODE; -- stop Input
perr : NODE; -- Parity Error Input
req64 : NODE; -- Request 64 bit
ack64 : NODE; -- Acknowledge 64 bit
-- Output Enables for PCI Signals
par_oe : NODE; -- PAR Output Enable
par_oeR : DFFE;
req64_oe : NODE; -- irdy Output enable
frame_oe : NODE; -- Frame Output Enable
irdy_oe : NODE; -- irdy Output enable
perr_oe_R : DFFE; -- PERR Output Enabel Register
-- Registered Active High PCI Signals
ad_IR_address[31..0] : DFFE; -- AD Input Register for Address
low_ad_IR_data[31..0] : DFFE; -- AD Input Register for Data
high_ad_IR_data[31..0] : DFFE; -- AD Input Register for Data
cben_IR_address[3..0] : DFFE; -- CBEN Input Register
low_cben_IR_data[3..0] : DFFE; -- CBEN Input Register
high_cben_IR_data[3..0] : DFFE; -- CBEN Input Register
-- Active High Output Registers for PCI Signals
low_ad_OR[31..0] : DFFE; -- AD Output Register
high_ad_OR[63..32] : DFFE; -- AD Output Register
low_cben_or[3..0] : DFFE; -- CBEN Output Register
high_cben_or[3..0] : DFFE; -- CBEN Output Register
par_OR : DFFE; -- PAR Output Register
par_OR64 : DFFE; -- PAR64 Output Register
frame_out : Node; -- Frame Output Signal
irdy_out : Node; -- Irdy Output Signal
req64_out : Node; -- Request 64 bit output signal
inta_OR : DFFE; -- Interrup A Output Register
req_out : NODE; -- Request Output Register
-- PCI Signals Tristate Buffers
ad_tri[63..0] : TRI; -- AD Tristate buffer
ad_tri_oe : NODE;
cbe_tri[7..0] : TRI; -- CBEN Tristate Buffer
-- Active High PCI Output Signals
-- Parity Checking Signals
-- Parity Generator Signals
par_gen_out : NODE; -- Parity Output from Parity Generator
par_gen_out64 : NODE; -- Parity Output from Parity Generator
-- Target Outputs
trg_serr_vld : LCELL;--NODE; -- SERR Error is valid
trg_perr_vld : NODE; -- Parity Error is valid
trg_perr_oe : NODE; -- PERR Output Enable
trg_par_oe : NODE; -- PAR Output Enable
--6/8 low_trg_dat_out[31..0]: NODE; -- Target Output Data to AD Output Register
-- low_trg_dat_out_lc1[31..0] : LCELL;
-- high_trg_dat_out[31..0]: NODE; -- Target Output Data to AD Output Register
-- trg_ad_ce : NODE; -- Target AD Output Registers clock Enable
trg_ad_oe : NODE; -- Target AD OE Output
trg_ad_sel : LCELL; -- AD Output Mux Select
-- ack64_oe : NODE; -- Ack64 Output Enable
ack64_out : NODE; -- Acknowledge 64 bit output signal
targ_oeR : NODE; -- Target Control Signals Output Enable
trdy_out : NODE; -- PCI Target Ready Output
devsel_out : NODE; -- PCI Device Select Output
stop_out : NODE; -- PCI Stop Output
serr_out : NODE; -- SERR Output Register
trg_ad_IR_ce_A : LCELL;--NODE; -- Target AD/BE Clock Enable- Address
trg_ad_IR_ce_D : LCELL;--NODE; -- Target AD/BE Clock Enable- Data
trg_cben_IR_ce_A : LCELL;--NODE; -- Target AD/BE Clock Enable- Address
trg_cben_IR_ce_D : LCELL;--NODE; -- Target AD/BE Clock Enable- Data
trg_low_data_out[31..0] : NODE; -- Target Local Side Low Output Data to AD Output Register
trg_high_data_out[31..0]: NODE; -- Target Local Side Low Output Data to AD Output Register
trg_cfg_dat_out[31..0] : NODE; -- Target Configuration data Output to AD Output Register
trg_cfg_cyc_out : NODE; -- Target Configuratiob Cycle Indicator
trg_hr_dat_sel : NODE; -- Target Holding Register Select Signal
trg_dati_HR_ena : NODE; -- Target Holding Register Enable Signal
trg_64_trans_out : NODE;
-- trg_adr_phase_out : NODE;
-- junk : node;
perr_rep_set : NODE;
perr_det_set : NODE;
serr_sig_set : NODE;
perr_out : Node;
io_ena : NODE; -- I/O Space Enable
mem_ena : NODE; -- Memory Space Enable
mstr_ena : NODE; -- Bus Master Enable
mwi_ena : NODE; -- Memory Write and Invalidate Enable
perr_ena : NODE; -- Pariy Error Response Enable
serr_ena : NODE; -- SERR Enable
perr_rep : NODE; -- Data Parity Error Signaled
tabort_sig : NODE; -- Signaled Target Abort
tabort_rcvd : NODE; -- Recieved Target Abort
mabort_rcvd : NODE; -- Recieved Master Abort
serr_sig : NODE; -- Signaled SERR
perr_det : NODE; -- Detected Parity Error
lat_dat[7..0] : NODE; -- Latency Timer data
-- cache[7..0] : NODE; -- Cache Line Register data
mstr_low_data_out[31..0]: NODE; -- Master Output Data to AD Output Register
mstr_high_data_out[31..0]: NODE; -- Master Output Data to AD Output Register
mstr_hr_dat_sel : NODE; -- Target Holding Register Select Signal
mstr_trg_hr_dat_sel : LCELL;
hi_low_sel : LCELL;--NODE;
mstr_dati_HR_ena : NODE; -- Target Holding Register Enable Signal
--6/8 low_mstr_dat_out[31..0] : NODE;
-- high_mstr_dat_out[31..0] : NODE;
mstr_ADOR_ena : LCELL;--NODE;
mstr_ad_oe : NODE; -- Master AD OE Output
mstr_ad_sel : LCELL; -- Master AD Output Mux Select
-- mstr_trg_ad_sel : LCELL;
mstr_ad_IR_ce_D : LCELL;--NODE; -- AD Input Register Clock Enable
mstr_cbe_oe : NODE; -- Master cbe Output enable
mstr_low_cbe_out[3..0] : NODE; -- Master Cbe output
mstr_high_cbe_out[3..0] : NODE; -- Master Cbe output
mstr_cbe_ce : LCELL;--NODE; -- master CBE Clock Enable
mstr_hr_cbe_sel : LCELL;--NODE;
mstr_cbe_HR_ena : LCELL;--NODE;
low_mstr_cbe_out[3..0] : NODE;
high_mstr_cbe_out[3..0] : NODE;
targ_abrt_set : Node;
mstr_abrt_set : NODE;
-- perr_vld : NODE;
-- stat_reg[5..0] : NODE;
low_data_out_HR[31..0] : DFFE; -- Low data holding register
low_data_out_hr_ena_d : NODE;
low_cbe_out_HR[3..0] : DFFE; -- Low Command Byte Enables holding register
high_data_out_HR[31..0] : DFFE; -- Low data holding register
high_cbe_out_HR[3..0] : DFFE; -- Low Command Byte Enables holding register
-- Local Master Active High Inputs
lm_last : NODE;
-- lm_adr64 : NODE;
lm_req64 : NODE;
lm_req32 : NODE;
lm_adr_ack : NODE;
-- Master Parity Signals
mstr_perr_vld : NODE; -- master Parity Error valid
mstr_perr_oe : NODE; -- PERR Output Enable
mstr_par_oe : NODE; -- PAR Output Enable
mstr_actv : NODE;
mstr_dac_decode : NODE;
trg_ADOR_ena : LCELL;--node;
ador_hi_dena : LCELL;--node;
m_ador_hi_dena : node;
mstr_hi_low_sel : LCELL;--node;
-- mstr_trg_hi_low_sel : LCELL;
--ad_ce : node;
-- mstr_MS_ENA : node;
-- mstr_MW_LXFR : node;
-- mstr_adr_vld : node;
-- mstr_wr_dxfr : NODE; -- Master Write Data Transfer
ad_IR_ce_data : LCELL;--node;
ad_IR_ce_address : LCELL;--node;
cben_IR_ce_data : LCELL;--node;
cben_IR_ce_address : LCELL;--node;
trg_low_ad_out_sel :node;
-- mstr_low_ad_out_sel :node;
mstr_trg_low_ad_out_sel : node;
--OPTIMIZATION high_low_ad_out_sel :node;
-- parity_ad_ir_ce_address : NODE;
-- parity_cben_ir_ce_address : NODE;
IF (TARGET_DEVICE == "EPF10K100EFC484") GENERATE
ad_ce[20..0] : LCELL;
ELSE GENERATE
IF (TARGET_DEVICE == "EPF10K50EFC484") GENERATE
ad_ce[26..0] : LCELL;
ELSE GENERATE
IF (TARGET_DEVICE == "EPF10K200EFC672") GENERATE
ad_ce[19..0] : LCELL;
ELSE GENERATE
IF (TARGET_DEVICE == "EPF10K130EFC484") GENERATE
ad_ce[19..0] : LCELL;
ELSE GENERATE
IF (TARGET_DEVICE == "NEW") GENERATE
ad_ce[63..0] : LCELL;
ELSE GENERATE
ad_ce[63..0] : LCELL;
END GENERATE;
END GENERATE;
END GENERATE;
END GENERATE;
END GENERATE;
--ad_ce : node;
ad_ce_nc : node;
ad_ce_lc : NODE;
low_ad_out[31..0] : NODE; -- AD Data MUX Ouput
low_ad_out_lc1[31..0] : LCELL;
low_ad_out_lc2[31..0] : LCELL;
-- low_ad_out_lc3[31..0] : LCELL;
mstr_trg_low : NODE;
high_ad_out[31..0] : NODE; -- AD Data MUX Ouput
high_ad_out_lc[31..0] : LCELL;
mstr_trg_hi_ad : LCELL;
--Local Data Out Signals
lt_ldata_ackn : NODE; -- Target Data Acknowledge
lt_hdata_ackn : NODE;
lm_ldata_ackn : NODE;
lm_hdata_ackn : NODE;
l_ldat_ack : NODE;
l_hdat_ack : NODE;
local_dat_sel : LCELL;--NODE;
lt_sel_w : NODE;
--jot mstr_hr_adr_sel : node;
mstr_64_trans_out : node;
mstr_ad_ir_ce_a : node;
mstr_cben_ir_ce_a : node;
mstr_cben_ir_ce_d : LCELL;--NODE;
-- 64bit_PCI : node;
-- Local Side Configuration Space Support
lcfg_adr[7..0] : NODE; -- Local Configuration Address
lcfg_ben[3..0] : NODE; -- Local Configuration Byte enables
lcfg_dati[31..0] : NODE; -- Local Configuration Data Input Bus
lcfg_adr_vld : NODE; -- Local Configuration Address Valid
lcfg_dat_vld : NODE; -- Local Configuration data Valid
lcfg_dato[31..0] : NODE; -- Local Configuration Data Output
-- trg_dac_sr : NODE;
BEGIN
lcfg_adr[7..0] = GND; -- Local Configuration Address
lcfg_ben[3..0] = GND; -- Local Configuration Byte enables
lcfg_dati[31..0] = GND; -- Local Configuration Data Input Bus
lcfg_adr_vld = GND; -- Local Configuration Address Valid
lcfg_dat_vld = GND; -- Local Configuration data Valid
lcfg_dato[31..0] = lcfg_dato[31..0]; -- Local Configuration Data Output
ASSERT REPORT "Compiling Altera's pci_c MegaCore. % " REVISION
SEVERITY INFO;
--
-- Instantiate Parity Checker par_chk.tdf
--
parity_chk.clk = clk; -- PCI clk Input
parity_chk.rstn = rstn; -- PCI rstn Input
parity_chk.par = par; -- PCI par signal
parity_chk.par64 = par64; -- PCI par64 signal
--JOT parity_chk.low_ad_IR[31..0] = (low_ad_IR_data[31..0] & ad_IR_ce_data)
--JOT # (ad_IR_address[31..0] & ad_IR_ce_address);-- PCI AD Bus Input Registers
--JOT parity_chk.low_cben_IR[3..0]= (low_cben_IR_data[3..0] & cben_IR_ce_data)
--JOT # (cben_IR_address[3..0] & cben_IR_ce_address);-- PCI CBE Bus Input Registers -- PCI CBEN Bus Input Registers
parity_chk.trg_64_trans_out = trg_64_trans_out;
parity_chk.mstr_64_trans_out = mstr_64_trans_out;
--jot parity_chk.trg_adr_phase_out = trg_adr_phase_out;
--jot parity_chk.lm_adr_ackn = lm_adr_ackn;
parity_chk.low_ad_IR_addr[31..0] = (ad_IR_address[31..0]);-- & parity_ad_ir_ce_address);-- PCI AD Bus Input Registers
parity_chk.low_cben_IR_addr[3..0] = (cben_IR_address[3..0]);-- & parity_cben_ir_ce_address);-- PCI CBE Bus Input Registers -- PCI CBEN Bus Input Registers
-- parity_ad_ir_ce_address = (ad_IR_ce_address or trg_adr_phase_out);
-- parity_cben_ir_ce_address = (cben_IR_ce_address or trg_adr_phase_out);
parity_chk.low_ad_IR[31..0] = (low_ad_IR_data[31..0] %& ad_IR_ce_data%); -- PCI AD Bus Input Registers
parity_chk.low_cben_IR[3..0] = (low_cben_IR_data[3..0] %& cben_IR_ce_data%); -- PCI CBEN Bus Input Registers
parity_chk.high_ad_IR[31..0] = (high_ad_IR_data[31..0]);-- and not trg_cfg_cyc_out %& ad_IR_ce_data%); -- PCI AD Bus Input Registers
parity_chk.high_cben_IR[3..0] = (high_cben_IR_data[3..0] %& cben_IR_ce_data%); -- PCI CBE Bus Input Registers -- PCI CBEN Bus Input Registers
parity_chk.perr_ena = perr_ena; -- Configuration Command Register Parity Enable
parity_chk.serr_ena = serr_ena; -- Configuration Command Register System Error Enable
parity_chk.mstr_perr_vld = mstr_perr_vld; -- Master Data Parity error valid
parity_chk.targ_perr_vld = trg_perr_vld; -- Target Data Parity error Valid
parity_chk.targ_serr_vld = trg_serr_vld; -- Target System Error valid
perr_det_set = parity_chk.perr_det_set; -- PERR Detect Set, Config Status Register Bit 15 Set
serr_sig_set = parity_chk.serr_sig_set; -- System Error Signaled Set
perr_out = parity_chk.perr_out; -- Parity Error Output
serr_out = parity_chk.serr_out; -- System Error Output
-- ************************************************************************
-- **** Instantiate the pcic_pg.tdf ****
-- ************************************************************************
parity_gen.data[31..0] = low_ad_OR[31..0]; -- Data Input
parity_gen.cbeN[3..0] = cben[3..0]; -- Command/Byte Enable
--JOT parity_gen.cbeN[3..0] = low_cben_or[3..0]; -- Command/Byte Enable
par_gen_out = parity_gen.parity; -- Parity Output
parity_gen64.data[31..0] = high_ad_OR[63..32]; -- Data Input
parity_gen64.cbeN[3..0] = cben[7..4]; -- Command/Byte Enable
par_gen_out64 = parity_gen64.parity; -- Parity Output
-- Parity Checking Logic
-- pchk_ena = cfg_pchk_ena; -- This will tell if parity_chk output is valid
-- pchk_error = par xor par_chk_out; -- Check if parity Input matches Parity Expected
-- Set PERRN (Driven During Master Reads and Target Writes)
--
-- Instantiate the target Module
--
-- PCI Signal Inputs
trg.clk = clk; -- PCI Clock
trg.rstn = rstn; -- PCI Reset
trg.ad_IR_address[31..0] = ad_IR_address[31..0]; -- AD Input Registers
trg.ad_ir_data[31..0] = low_ad_ir_data[31..0];
trg.cben_IR_address[3..0] = cben_IR_address[3..0]; -- Command/Byte Enable Input Registers
trg.cben_ir_data[3..0] = low_cben_ir_data[3..0];
trg.frame = frame; -- Active High FRAMEn Input
trg.irdy = irdy; -- Active High IRDYn Input
trg.idsel = idsel; -- IDSEL Input Register
trg.req64 = req64;
-- Local Side Inputs
IF (DUAL_ADDRESS_ENA == "NO") GENERATE
trg.low_lt_dati[31..0] = l_dati[31..0]; -- Local Target Data Input
trg.high_lt_dati[31..0] = l_dati[63..32]; -- Local Target Data Input
ELSE GENERATE
trg.low_lt_dati[31..0] = l_adi[31..0]; -- Local Target Data Input
trg.high_lt_dati[31..0] = l_adi[63..32]; -- Local Target Data Input
END GENERATE;
trg.lt_rdyn = lt_rdyn; -- Local Target Ready Input
trg.lt_discn = lt_discn; -- Local Target Disconnect Input
trg.lt_abortn = lt_abortn; -- Local Target Abort Input
-- trg.64bit_PCI = 64bit_PCI ; -- Indicates a pure 64bit system
-- Input from Parity Checker
-- trg.pchk_error = pchk_error; -- Parity Checker Not same as PAR detected
trg.perr_rep_set = perr_rep_set; -- Data Parity Error Signaled
trg.perr_det_set = perr_det_set; -- Parity Error Detected
trg.serr_sig_set = serr_sig_set; -- System Parity Error Signaled
trg.mstr_dac_decode = mstr_dac_decode;
trg.mstr_actv = mstr_actv; -- Master is Active. Has PCI Bus
trg.mstr_abrt_set = mstr_abrt_set; -- Master Abort Set
trg.targ_abrt_set = targ_abrt_set; -- Target Abort Set
trg.lm_ackn = lm_ackn;
trg_serr_vld = trg.serr_vld; -- SERR Valid
trg_perr_vld = trg.perr_vld; -- Parity Error was detected
trg_perr_oe = trg.perr_oe; -- PERR Output Enable
trg_par_oe = trg.par_oe; -- PAR Output Enable
-- Local Side Outputs
l_adro[63..0] = trg.lt_adr[63..0]; -- Local Target Address
l_cmdo[3..0] = trg.lt_cmd[3..0]; -- Local Target Command
lt_ldata_ackn = trg.lt_ldata_ackn;
lt_hdata_ackn = trg.lt_hdata_ackn;
lt_sel_w = trg.lt_sel_w;
-- lt_lackn = trg.lt_lackn; -- Target Low Data Acknowledge
-- lt_hackn = trg.lt_hackn; -- Target High Data Acknowledge
lt_tsr[11..0] = trg.lt_tsr[11..0]; -- Local Target Transaction Status Registers
lt_dxfrn = trg.lt_dxfrn; -- Local Target Data Transfer
lt_framen = trg.lt_framen; -- Local Target Frame
lt_ackn = trg.lt_ackn; -- Local target Acknowledge
-- AD Bus Controls
-- trg_ad_ce = trg.ad_ce; -- Target AD Output Registers clock Enable
trg_ad_oe = trg.ad_oe; -- Target AD OE Output
trg_ad_sel = trg.ad_sel; -- AD Output Mux Select
-- trg_dac_sr = trg.dac_sr_out;
trg_ad_IR_ce_D = trg.ad_IR_ce_D; -- Target Address Clock Enable
trg_ad_IR_ce_A = trg.ad_IR_ce_A; -- Target Data Clock Enable
trg_cben_IR_ce_D = trg.cben_IR_ce_D; -- Target Address Clock Enable
trg_cben_IR_ce_A = trg.cben_IR_ce_A; -- Target Data Clock Enable
trg_low_data_out[31..0] = trg.low_data_out[31..0];
trg_high_data_out[31..0] = trg.high_data_out[31..0];
trg_cfg_dat_out[31..0] = trg.cfg_dat_out[31..0]; -- Configuration data Output to AD Output Register
trg_cfg_cyc_out = trg.cfg_cyc_out; -- Configuratiob Cycle Indicator
trg_hr_dat_sel = trg.hr_dat_sel; -- Holding Register Select Signal
trg_dati_HR_ena = trg.dati_HR_ena; -- Holding Register Enable Signal
hi_low_sel = trg.hi_low_sel;
trg_64_trans_out = trg.64_trans_out;
-- trg_adr_phase_out = trg.adr_phase_out;
-- Target Control Signal Outputs
targ_oeR = trg.targ_oeR; -- Output Enable Signal for Target Controls
trdy_out = trg.trdy_out; -- PCI Target Ready Output
devsel_out = trg.devsel_out; -- PCI Device Select Output
stop_out = trg.stop_out; -- PCI Stop Output
ack64_out = trg.ack64_out;
-- Local Command Register Outputs
io_ena = trg.io_ena; -- I/O Space Enable
mem_ena = trg.mem_ena; -- Memory Space Enable
mstr_ena = trg.mstr_ena; -- Bus Master Enable
mwi_ena = trg.mwi_ena; -- Memory Write and Invalidate Enable
perr_ena = trg.perr_ena; -- Pariy Error Response Enable
serr_ena = trg.serr_ena; -- SERR Enable
-- Local Status Register Outputs
perr_rep = trg.cfg_perr_rep; -- Data Parity Error Signaled
tabort_sig = trg.cfg_tabrt_sig; -- Signaled Target Abort
tabort_rcvd = trg.cfg_tabrt_rcvd; -- Recieved Target Abort
mabort_rcvd = trg.cfg_mabrt_rcvd; -- Recieved Master Abort
serr_sig = trg.cfg_serr_sig; -- Signaled SERR
perr_det = trg.cfg_perr_det; -- Detected Parity Error
-- Other Local Configuration Register Outputs
lat_dat[7..0] = trg.lat_dat[7..0]; -- Latency Timer Register Data
cache[7..0] = trg.cache_dat[7..0]; -- Cache Line Register Data
-- bar_hit[5..0] = trg.base_hit[5..0]; -- Base Address Register Comparison Outputs
-- Local Side Configuration Space Support
trg.lcfg_adr[7..0] = lcfg_adr[7..0]; -- Local Configuration Address
trg.lcfg_ben[3..0] = lcfg_ben[3..0]; -- Local Configuration Byte enables
trg.lcfg_dat_in[31..0] = lcfg_dati[31..0]; -- Local Configuration Data Input Bus
trg.lcfg_adr_vld = lcfg_adr_vld; -- Local Configuration Address Valid
trg.lcfg_dat_vld = lcfg_dat_vld; -- Local Configuration data Valid
lcfg_dato[31..0] = trg.lcfg_dat_out[31..0];-- Local Configuration Data Output
-- AD_CE addition
trg_ADOR_ena = trg.ADOR_ena;
ador_hi_dena = trg.ador_hi_dena;
m_ador_hi_dena = mstr.ador_hi_dena;
mstr_hi_low_sel = mstr.hi_low_sel;
-- ***************************************************************************
-- ************************************************************************
-- **** Instantiate pcic_m.tdf ****
-- ************************************************************************
-- PCI Inputs
mstr.clk = clk; -- PCI Clock
mstr.rstn = rstn; -- PCI Restet
mstr.gnt = gnt; -- Active High PCI Grant Signal
mstr.frame = frame; -- Active High FRAMEn Input
mstr.irdy = irdy; -- Active High IRDYn INPUT
mstr.trdy = trdy; -- Active High TRDYn Input
mstr.devsel = devsel; -- Active High DEVSELn Input
mstr.stop = stop; -- Active High STOPn Input
mstr.ack64 = ack64;
mstr.perr = perr; -- Active high
-- Configuration Space Inputs
mstr.mstr_ena = mstr_ena ; -- Master Enable
mstr.lat_dat[7..0] = lat_dat[7..0] ; -- Latency Timer Register Data
-- Local Side Inputs
mstr.lm_req64 = lm_req64 ; -- Local Side Master Access Request Signal
mstr.lm_req32 = lm_req32 ; -- Local Side Master Access Request Signal
-- mstr.lm_adr64 = lm_adr64 ; -- Local Side Master 64-bit Address Request Signal
mstr.lm_last = lm_last ; -- Local Side Master Access Request Signal
mstr.lm_rdyn = lm_rdyn ; -- Local Side Master Data Ready Input
IF (DUAL_ADDRESS_ENA == "NO") GENERATE
mstr.low_lm_dati[31..0] = l_dati[31..0] ; -- Local Side Master Address/Data Bus
mstr.high_lm_dati[31..0]= l_dati[63..32]; -- Local Side Master Address/Data Bus
mstr.low_lm_beni[3..0] = l_beni[3..0] ; -- Local Side Master Command/Byte Enables
mstr.high_lm_beni[3..0] = l_beni[7..4] ; -- Local Side Master Command/Byte Enables
mstr.lm_adri[31..0] = l_adri[31..0] ; -- Local Side Master Address/Data Bus
mstr.lm_cmd[3..0] = l_cmdi[3..0] ; -- Local Side Command Signal
ELSE GENERATE
mstr.low_lm_dati[31..0] = l_adi[31..0] ; -- Local Side Master Address/Data Bus
mstr.high_lm_dati[31..0]= l_adi[63..32]; -- Local Side Master Address/Data Bus
mstr.low_lm_beni[3..0] = l_cbeni[3..0] ; -- Local Side Master Command/Byte Enables
mstr.high_lm_beni[3..0] = l_cbeni[7..4] ; -- Local Side Master Command/Byte Enables
-- mstr.lm_adri[31..0] = l_adi[31..0] ; -- Local Side Master Address/Data Bus
-- mstr.lm_cmd[3..0] = l_cbeni[3..0] ; -- Local Side Command Signal
END GENERATE;
-- mstr.64bit_PCI = 64bit_PCI ; -- Indicates a pure 64bit system
-- PCI Outputs
-- AD Bus Controls
mstr_low_data_out[31..0] = mstr.low_data_out[31..0]; -- Master Output Data to AD Output Register
mstr_high_data_out[31..0] = mstr.high_data_out[31..0];-- Master Output Data to AD Output Register
mstr_ad_oe = mstr.ad_oe ; -- Master AD OE Output
mstr_ad_sel = mstr.ad_sel ; -- Master AD Output Mux Select
mstr_ad_IR_ce_D = mstr.ad_IR_ce_D ; -- AD Input Register Clock Enable
mstr_hr_dat_sel = mstr.hr_dat_sel ;
mstr_dati_HR_ena = mstr.dati_HR_ena ;
mstr_ADOR_ena = mstr.ADOR_ena ;
--jot mstr_hr_adr_sel = mstr.hr_adr_sel;
mstr_64_trans_out = mstr.64_trans_out ;
mstr_ad_ir_ce_a = mstr.ad_ir_ce_a;
mstr_cben_ir_ce_a = mstr.cben_ir_ce_a;
mstr_cben_ir_ce_d = mstr.cben_ir_ce_d;
-- Command/byte enable Bus Signals
mstr_cbe_ce = mstr.cbe_ce ; -- Command/Byte Enable Clock Enable
mstr_low_cbe_out[3..0] = mstr.low_cbe_out[3..0]; -- Command/Byte Enable Output Registers
mstr_high_cbe_out[3..0] = mstr.high_cbe_out[3..0]; -- Command/Byte Enable Output Registers
mstr_hr_cbe_sel = mstr.hr_cbe_sel ;
mstr_cbe_HR_ena = mstr.cbe_HR_ena ;
mstr_cbe_oe = mstr.cbe_oe ; -- Command/Byte Enable Output Enable
-- Hand Shake Signals
frame_out = mstr.frame_out ; -- FRAMEn Output Register
frame_oe = mstr.frame_oe ; -- Frame Output Enable
irdy_out = mstr.irdy_out ; -- IRDYn Output Register
irdy_oe = mstr.irdy_oe ; -- IRDYn Output Enable
req64_out = mstr.req64_out ; -- IRDYn Output Register
req64_oe = mstr.req64_oe ; -- IRDYn Output Enable
req_out = mstr.req_out ; -- PCI Bus Request Output Register
-- Parity Signals
mstr_perr_vld = mstr.perr_vld ; -- Parity Error was detected
mstr_perr_oe = mstr.perr_oe ; -- PERR Output Enable
mstr_par_oe = mstr.par_oe ; -- PAR Output Enable
-- Configuration Space Outputs
perr_rep_set = mstr.perr_rep_set ; -- Set Command Register Target Abort Recieved Bit
targ_abrt_set = mstr.targ_abrt_set ; -- Set Command Register Target Abort Recieved Bit
mstr_abrt_set = mstr.mstr_abrt_set ; -- Set Command Regsiter Master Abort Recieved Bit
-- Local Side Outputs
lm_adr_ack = mstr.lm_adr_ack ; -- Local Master Address Acknowledge
lm_ackn = mstr.lm_ackn ; -- PCI/B Ready/Acknowledge Signal
-- trdyrn = mstr.trdyrn ; -- This is a registered version of PCI trdyn signal
lm_ldata_ackn = mstr.lm_ldata_ackn;
lm_hdata_ackn = mstr.lm_hdata_ackn;
lm_dxfrn = mstr.lm_dxfrn;
lm_tsr[9..0] = mstr.lm_tsr[9..0] ; -- Master Transaction Status Registers
mstr_actv = mstr.mstr_actv ; -- Master is Active. Has PCI Bus
mstr_dac_decode = mstr.dac_decode_out ; -- Dual Address decode
-- *************************************************************************************************
-- junk = trg_adr_phase_out or mstr_actv;
perr = NOT perrn; -- Active high perr Input
perr_oe_R.clk = clk; -- PERRn Output Enable Register
perr_oe_R.clrn = rstn;
perr_oe_R = trg_perr_oe OR mstr_perr_oe;
perrn = TRI(NOT perr_out, perr_oe_R); -- PERRn Output
-- SERRn Signal
serrn = OPNDRN(NOT serr_out); -- SERRn Output
-- par Signals
par_or.clk = clk ; -- par output regsister
par_or.clrn = rstn;
par_or = par_gen_out;
par_or64.clk = clk ; -- par output regsister
par_or64.clrn = rstn;
-- par_or64.ena = not trg_cfg_cyc_out;
par_or64 = par_gen_out64;
par_oeR.clk = clk;
par_oeR.clrn = rstn;
par_oeR = trg_par_oe OR mstr_par_oe;
par_oe = par_oeR;
par = TRI(par_or, par_oe); -- par Output
par64 = TRI(par_or64, par_oe); -- par64 Output
-- AD OUTPUT Bus Signals
l_dato[31..0] = low_ad_IR_data[31..0]; -- Local Data Output
-- Local Data Output
l_dato[63..32] = (high_ad_IR_data[31..0] and local_dat_sel)
OR (low_ad_IR_data[31..0] and not local_dat_sel);
local_dat_sel = (not lt_hdata_ackn and not lt_ldata_ackn and lt_sel_w)
OR (not lm_hdata_ackn and not lm_ldata_ackn and not lt_sel_w and mstr_64_trans_out);
--jot l_ldat_ackn = (lt_ldata_ackn and lt_sel_w)
--jot OR (lm_ldata_ackn and not lt_sel_w);
--jot l_hdat_ackn = (lt_hdata_ackn and lt_sel_w)
--jot OR (lm_hdata_ackn and not lt_sel_w);
l_ldat_ack = (not lt_ldata_ackn and lt_sel_w)
OR (not lm_ldata_ackn and not lt_sel_w);
l_hdat_ack = (not lt_hdata_ackn and lt_sel_w)
OR (not lm_hdata_ackn and not lt_sel_w);
l_ldat_ackn = not l_ldat_ack;
l_hdat_ackn = not l_hdat_ack;
l_beno[3..0] = low_cben_IR_data[3..0]; -- Local Data Output
l_beno[7..4] = (high_cben_IR_data[3..0] and local_dat_sel)
OR (low_cben_IR_data[3..0] and not local_dat_sel); -- Local Data Output
ad_ce_nc = lcell (trg_ADOR_ena
OR mstr_ADOR_ena);
-- ad_ce = (trdy and irdy) OR ad_ce_nc;
----------LOW Data Output----------------
-- OPTIMIZATION low_trg_dat_out[31..0] = (trg_low_data_out[31..0] and not trg_cfg_cyc_out and not trg_hr_dat_sel)--low_trg_dat_out_lc1[]
-- OPTIMIZATION OR (low_data_out_HR[31..0] and not trg_cfg_cyc_out and trg_hr_dat_sel); -- 4 INPUTS
-- OR (trg_cfg_dat_out[31..0] and trg_cfg_cyc_out);
--6/8 low_trg_dat_out[31..0] = (trg_low_data_out[31..0] and not trg_hr_dat_sel)--low_trg_dat_out_lc1[]
--6/8 OR (low_data_out_HR[31..0] and trg_hr_dat_sel); -- 4 INPUTS
--6/8 low_trg_dat_out[31..0] = (trg_low_data_out[31..0] and not mstr_trg_hr_dat_sel)--low_trg_dat_out_lc1[] -- trg_low_data_out = l_adi[31..0]
--6/8 OR (low_data_out_HR[31..0] and mstr_trg_hr_dat_sel); -- 4 INPUTS
--OPTIMIZATION low_trg_dat_out_lc1[] = (trg_low_data_out[31..0] and not trg_cfg_cyc_out and not trg_hr_dat_sel)
--OPTIMIZATION OR (low_data_out_HR[31..0] and not trg_cfg_cyc_out and trg_hr_dat_sel);
--6/8 low_mstr_dat_out[31..0] = (mstr_low_data_out[31..0] and not mstr_hr_dat_sel)
--6/8 OR (low_data_out_HR[31..0] and mstr_hr_dat_sel);
--6/8 low_mstr_dat_out[31..0] = (mstr_low_data_out[31..0] and not mstr_trg_hr_dat_sel) -- mstr_low_data_out = l_adi[31..0]
--6/8 OR (low_data_out_HR[31..0] and mstr_trg_hr_dat_sel);
low_mstr_cbe_out[] = (mstr_low_cbe_out[3..0] and not mstr_hr_cbe_sel and not mstr_hi_low_sel)
OR (low_cbe_out_HR[3..0] and mstr_hr_cbe_sel and not mstr_hi_low_sel)
or (high_cbe_out_HR[3..0] and mstr_hi_low_sel);
low_data_out_HR[] = (trg_low_data_out[] and trg_ad_sel )
OR (mstr_low_data_out[] and mstr_ad_sel);
low_data_out_HR[].clk = clk;
low_data_out_HR[].clrn = rstn;
low_data_out_HR[].ena = low_data_out_hr_ena_d;-- Holding Register Enable Signal
low_data_out_hr_ena_d = LCELL(trg_dati_HR_ena # mstr_dati_HR_ena);
low_cbe_out_HR[] = mstr_low_cbe_out[];
low_cbe_out_HR[].clk = clk;
low_cbe_out_HR[].clrn = rstn;
low_cbe_out_HR[].ena = mstr_cbe_HR_ena;
--6/8 low_ad_out_lc1[] = ((low_trg_dat_out[31..0] OR (trg_cfg_dat_out[31..0] and trg_cfg_cyc_out)) and trg_low_ad_out_sel)
--6/8 OR (low_mstr_dat_out[31..0] and mstr_low_ad_out_sel);
low_ad_out_lc1[] = (trg_cfg_dat_out[31..0] and trg_cfg_cyc_out and trg_low_ad_out_sel) OR low_ad_out_lc2[];
--OPTIMIZATION low_ad_out[] = low_ad_out_lc1[]
--OPTIMIZATION OR (high_ad_or[63..32] and high_low_ad_out_sel);
--6/8 low_ad_out[] = low_ad_out_lc1[]
--6/8 OR (high_ad_or[63..32] and not(trg_low_ad_out_sel or mstr_low_ad_out_sel));-- high_low_ad_out_sel);
low_ad_out_lc2[] = (low_data_out_HR[] and mstr_trg_hr_dat_sel and mstr_trg_low_ad_out_sel)
OR (high_ad_or[63..32] and not(mstr_trg_low_ad_out_sel));-- and not l_adro2);
-- OR (trg_high_data_out and not(mstr_trg_low_ad_out_sel) and l_adro2);-- high_low_ad_out_sel);
mstr_trg_low = LCELL(not mstr_trg_hr_dat_sel and mstr_trg_low_ad_out_sel and not trg_cfg_cyc_out);
low_ad_out[] = low_ad_out_lc1[]
OR ((trg_low_data_out[] or mstr_low_data_out[]) and mstr_trg_low);
--trg_low_data_out = mstr_low_data_out = l_adi[31..0]
mstr_trg_hr_dat_sel = mstr_hr_dat_sel or trg_hr_dat_sel;
-- mstr_trg_ad_sel = ((mstr_ad_sel or trg_ad_sel) and not trg_cfg_cyc_out);
-- mstr_trg_hi_low_sel = mstr_hi_low_sel or hi_low_sel;
trg_low_ad_out_sel = LCELL(trg_ad_sel and not hi_low_sel );
--6/8 mstr_low_ad_out_sel = LCELL(mstr_ad_sel and not mstr_hi_low_sel);
mstr_trg_low_ad_out_sel = LCELL((mstr_ad_sel or trg_ad_sel) and not (mstr_hi_low_sel or hi_low_sel));
--OPTIMIZATION high_low_ad_out_sel = (hi_low_sel or mstr_hi_low_sel);
IF (TARGET_DEVICE == "EPF10K100EFC484") GENERATE
ad_ce[9..0] = (trdy and irdy) or ad_ce_nc;
low_ad_or[1..0].ena = ad_ce0;
low_ad_or[4].ena = ad_ce0;
low_ad_or[3..2].ena = ad_ce1;
low_ad_or[11..10].ena = ad_ce1;
low_ad_or[7..5].ena = ad_ce2;
low_ad_or[9..8].ena = ad_ce3;
low_ad_or[12].ena = ad_ce3;
low_ad_or[13].ena = ad_ce4;
low_ad_or[17].ena = ad_ce4;
low_ad_or[16..15].ena = ad_ce5;
low_ad_or[20].ena = ad_ce5;
low_ad_or[14].ena = ad_ce6;
low_ad_or[18].ena = ad_ce6;
low_ad_or[21].ena = ad_ce6;
low_ad_or[23].ena = ad_ce6;
low_ad_or[19].ena = ad_ce7;
low_ad_or[24].ena = ad_ce7;
low_ad_or[29].ena = ad_ce7;
low_ad_or[30].ena = ad_ce7;
low_ad_or[22].ena = ad_ce8;
low_ad_or[26].ena = ad_ce8;
low_ad_or[25].ena = ad_ce9;
low_ad_or[28..27].ena = ad_ce9;
low_ad_or[31].ena = ad_ce9;
ELSE GENERATE
IF (TARGET_DEVICE == "EPF10K50EFC484") GENERATE
ad_ce[13..0] = (trdy and irdy) or ad_ce_nc;
low_ad_or[0].ena = ad_ce0;
low_ad_or[30].ena = ad_ce0;
low_ad_or[7].ena = ad_ce0;
low_ad_or[23].ena = ad_ce0;
low_ad_or[15].ena = ad_ce0;
low_ad_or[1].ena = ad_ce1;
low_ad_or[8].ena = ad_ce1;
low_ad_or[29].ena = ad_ce1;
low_ad_or[24].ena = ad_ce1;
low_ad_or[16].ena = ad_ce1;
low_ad_or[9].ena = ad_ce2;
low_ad_or[31].ena = ad_ce2;
low_ad_or[25].ena = ad_ce2;
low_ad_or[17].ena = ad_ce2;
low_ad_or[26].ena = ad_ce3;
low_ad_or[2].ena = ad_ce3;
low_ad_or[18].ena = ad_ce3;
low_ad_or[10].ena = ad_ce3;
low_ad_or[27].ena = ad_ce4;
low_ad_or[19].ena = ad_ce4;
low_ad_or[20].ena = ad_ce4;
low_ad_or[3].ena = ad_ce5;
low_ad_or[14].ena = ad_ce5;
low_ad_or[4].ena = ad_ce6;
low_ad_or[5].ena = ad_ce7;
low_ad_or[6].ena = ad_ce8;
low_ad_or[11].ena = ad_ce9;
low_ad_or[12].ena = ad_ce10;
low_ad_or[22].ena = ad_ce10;
low_ad_or[13].ena = ad_ce11;
low_ad_or[21].ena = ad_ce12;
low_ad_or[28].ena = ad_ce13;
ELSE GENERATE
IF (TARGET_DEVICE == "EPF10K200EFC672") GENERATE
ad_ce[9..0] = (trdy and irdy) or ad_ce_nc;
low_ad_or[1..0].ena = ad_ce0;
low_ad_or[5..2].ena = ad_ce1;
low_ad_or[8..6].ena = ad_ce2;
low_ad_or[11].ena = ad_ce2;
low_ad_or[10..9].ena = ad_ce3;
low_ad_or[13].ena = ad_ce3;
low_ad_or[15].ena = ad_ce3;
low_ad_or[12].ena = ad_ce4;
low_ad_or[14].ena = ad_ce4;
low_ad_or[17].ena = ad_ce4;
low_ad_or[19].ena = ad_ce4;
low_ad_or[16].ena = ad_ce5;
low_ad_or[18].ena = ad_ce5;
low_ad_or[20].ena = ad_ce5;
low_ad_or[21].ena = ad_ce6;
low_ad_or[23].ena = ad_ce6;
low_ad_or[26..25].ena = ad_ce6;
low_ad_or[22].ena = ad_ce7;
low_ad_or[28].ena = ad_ce7;
low_ad_or[30].ena = ad_ce7;
low_ad_or[27].ena = ad_ce8;
low_ad_or[24].ena = ad_ce8;
low_ad_or[31].ena = ad_ce9;
low_ad_or[29].ena = ad_ce9;
ELSE GENERATE
IF (TARGET_DEVICE == "EPF10K130EFC484") GENERATE
ad_ce[9..0] = (trdy and irdy) or ad_ce_nc;
low_ad_or[0].ena = ad_ce0;
low_ad_or[4].ena = ad_ce0;
low_ad_or[7].ena = ad_ce0;
low_ad_or[9].ena = ad_ce0;
low_ad_or[2..1].ena = ad_ce1;
low_ad_or[3].ena = ad_ce2;
low_ad_or[6..5].ena = ad_ce2;
low_ad_or[8].ena = ad_ce2;
low_ad_or[10].ena = ad_ce3;
low_ad_or[15..14].ena = ad_ce3;
low_ad_or[13..11].ena = ad_ce4;
low_ad_or[20].ena = ad_ce4;
low_ad_or[19..16].ena = ad_ce5;
low_ad_or[24..21].ena = ad_ce6;
low_ad_or[26..25].ena = ad_ce7;
low_ad_or[28].ena = ad_ce7;
low_ad_or[27].ena = ad_ce8;
low_ad_or[29].ena = ad_ce8;
low_ad_or[31..30].ena = ad_ce9;
ELSE GENERATE
IF (TARGET_DEVICE == "NEW") GENERATE
ad_ce[31..0] = (trdy and irdy) or ad_ce_nc;
low_ad_or[31..0].ena = ad_ce[31..0];
ELSE GENERATE
ad_ce[31..0] = (trdy and irdy) or ad_ce_nc;
low_ad_or[31..0].ena = ad_ce[31..0];
END GENERATE;
END GENERATE;
END GENERATE;
END GENERATE;
END GENERATE;
low_ad_OR[].clk = clk; -- AD Output Register
low_ad_OR[].clrn = rstn;
-- low_ad_OR[].ena = ad_ce;
low_ad_OR[] = low_ad_out[];
low_cben_or[].clk = clk;
low_cben_or[].clrn = rstn;
low_cben_or[].ena = mstr_cbe_ce;
low_cben_or[] = low_mstr_cbe_out[];
----------HIGH Data Output----------------
--OPTIMIZATION high_trg_dat_out[] = (trg_high_data_out[31..0] and (not trg_cfg_cyc_out and not trg_hr_dat_sel))
--OPTIMIZATION OR (high_data_out_HR[] and not trg_cfg_cyc_out and trg_hr_dat_sel);
--6/8 high_trg_dat_out[] = (trg_high_data_out[31..0] and not trg_hr_dat_sel)
--6/8 OR (high_data_out_HR[] and trg_hr_dat_sel);
--6/8 high_mstr_dat_out[] = (mstr_high_data_out[31..0] and not mstr_hr_dat_sel) #
--6/8 (high_data_out_HR[31..0] and mstr_hr_dat_sel);
--6/11 high_trg_dat_out[] = (trg_high_data_out[31..0] and not mstr_trg_hr_dat_sel)
--6/11 OR (high_data_out_HR[] and mstr_trg_hr_dat_sel);
--6/11 high_mstr_dat_out[] = (mstr_high_data_out[31..0] and not mstr_trg_hr_dat_sel) #
--6/11 (high_data_out_HR[31..0] and mstr_trg_hr_dat_sel);
high_mstr_cbe_out[] = (mstr_high_cbe_out[3..0] and not mstr_hr_cbe_sel) #
(high_cbe_out_HR[3..0] and mstr_hr_cbe_sel);
--6/8 high_data_out_HR[] = (trg_high_data_out[] and trg_ad_sel) #
--6/8 (mstr_high_data_out[] and mstr_ad_sel);
high_data_out_HR[] = (trg_high_data_out[] and trg_ad_sel) #
(mstr_high_data_out[] and mstr_ad_sel);
high_data_out_HR[].clk = clk;
high_data_out_HR[].clrn = rstn;
high_data_out_HR[].ena = LCELL(trg_dati_HR_ena # mstr_dati_HR_ena); -- Holding Register Enable Signal
high_cbe_out_HR[] = mstr_high_cbe_out[];
high_cbe_out_HR[].clk = clk;
high_cbe_out_HR[].clrn = rstn;
high_cbe_out_HR[].ena = mstr_cbe_HR_ena;
-- mstr_trg_ad_sel = (mstr_ad_sel or trg_ad_sel);
mstr_trg_hi_ad = (mstr_ad_sel or trg_ad_sel) and not mstr_trg_hr_dat_sel;
-- high_ad_out[] = high_trg_dat_out[31..0] and mstr_trg_ad_sel
-- OR high_mstr_dat_out[31..0] and mstr_trg_ad_sel;
high_ad_out_lc[] = (high_data_out_HR[] and mstr_trg_hr_dat_sel and (trg_ad_sel or mstr_ad_sel));
high_ad_out[] = ( ((trg_high_data_out[31..0] or mstr_high_data_out[]) and mstr_trg_hi_ad)
OR high_ad_out_lc[]
);
high_ad_OR[63..32].clk = clk; -- AD Output Register
high_ad_OR[63..32].clrn = rstn;
-- high_ad_OR[].ena = ad_ce and not adOR_hi_dena and not m_ador_hi_dena;
high_ad_OR[63..32] = high_ad_out[];
IF (TARGET_DEVICE == "EPF10K100EFC484") GENERATE
ad_ce_lc = LCELL(not adOR_hi_dena and not m_ador_hi_dena);
ad_ce[20..10] = ((trdy and irdy) or ad_ce_nc) AND ad_ce_lc;
-- ad_ce[21..10] = ((trdy and irdy) or ad_ce_nc) and (not adOR_hi_dena and not m_ador_hi_dena);
-- ad_ce[21..10] = ((trdy and irdy) and (not adOR_hi_dena and not m_ador_hi_dena))
-- OR LCELL((ad_ce_nc) and (not adOR_hi_dena and not m_ador_hi_dena));
%
adOR_hi_dena = not ((LR_PXFR_32 and not irdy and not direct_xfr)
OR (LR_PXFR and lt_rdynR and not direct_xfr));
= (not (LR_PXFR_32 and not irdy and not direct_xfr)
and not (LR_PXFR and lt_rdynR and not direct_xfr));
=
%
high_ad_or[34..32].ena = ad_ce10;
high_ad_or[37..35].ena = ad_ce11;
high_ad_or[38].ena = ad_ce12;
high_ad_or[40].ena = ad_ce12;
high_ad_or[39].ena = ad_ce13;
high_ad_or[41].ena = ad_ce13;
high_ad_or[44].ena = ad_ce13;
high_ad_or[47].ena = ad_ce13;
high_ad_or[43..42].ena = ad_ce14;
high_ad_or[45].ena = ad_ce14;
high_ad_or[46].ena = ad_ce15;
high_ad_or[50..48].ena = ad_ce15;
high_ad_or[54..51].ena = ad_ce16;
high_ad_or[58..55].ena = ad_ce17;
high_ad_or[59].ena = ad_ce18;
high_ad_or[62].ena = ad_ce18;
high_ad_or[61..60].ena = ad_ce19;
high_ad_or[63].ena = ad_ce20;
ELSE GENERATE
IF (TARGET_DEVICE == "EPF10K50EFC484") GENERATE
ad_ce_lc = LCELL(not adOR_hi_dena and not m_ador_hi_dena);
%ad_ce[32..14] = ((trdy and irdy) or ad_ce_nc) AND ad_ce_lc;
high_ad_or[32].ena = ad_ce14;
high_ad_or[34].ena = ad_ce14;
high_ad_or[33].ena = ad_ce15;
high_ad_or[36..35].ena = ad_ce16;
high_ad_or[38..37].ena = ad_ce17;
high_ad_or[39].ena = ad_ce18;
high_ad_or[40].ena = ad_ce19;
high_ad_or[42].ena = ad_ce19;
high_ad_or[41].ena = ad_ce20;
high_ad_or[43].ena = ad_ce20;
high_ad_or[45..44].ena = ad_ce21;
high_ad_or[47..46].ena = ad_ce22;
high_ad_or[49..48].ena = ad_ce23;
high_ad_or[50].ena = ad_ce24;
high_ad_or[52..51].ena = ad_ce25;
high_ad_or[54..53].ena = ad_ce26;
high_ad_or[56..55].ena = ad_ce27;
high_ad_or[57].ena = ad_ce28;
high_ad_or[63].ena = ad_ce29;
high_ad_or[59..58].ena = ad_ce30;
high_ad_or[60].ena = ad_ce31;
high_ad_or[62..61].ena = ad_ce32;%
ad_ce[26..14] = ((trdy and irdy) or ad_ce_nc) AND ad_ce_lc;
high_ad_or[32].ena = ad_ce14;
high_ad_or[36].ena = ad_ce14;
high_ad_or[35..33].ena = ad_ce15;
high_ad_or[37].ena = ad_ce15;
high_ad_or[41..38].ena = ad_ce16;
high_ad_or[43..42].ena = ad_ce17;
high_ad_or[45].ena = ad_ce17;
high_ad_or[44].ena = ad_ce18;
high_ad_or[48..46].ena = ad_ce18;
high_ad_or[52..49].ena = ad_ce19;
high_ad_or[54..53].ena = ad_ce20;
high_ad_or[56..55].ena = ad_ce21;
high_ad_or[57].ena = ad_ce22;
high_ad_or[63].ena = ad_ce23;
high_ad_or[59..58].ena = ad_ce24;
high_ad_or[60].ena = ad_ce25;
high_ad_or[62..61].ena = ad_ce26;
ELSE GENERATE
IF (TARGET_DEVICE == "EPF10K200EFC672") GENERATE
ad_ce_lc = LCELL(not adOR_hi_dena and not m_ador_hi_dena);
ad_ce[19..10] = ((trdy and irdy) or ad_ce_nc) AND ad_ce_lc;
high_ad_or[32].ena = ad_ce10;
high_ad_or[35].ena = ad_ce10;
high_ad_or[37].ena = ad_ce10;
high_ad_or[36].ena = ad_ce11;
high_ad_or[34..33].ena = ad_ce12;
high_ad_or[45].ena = ad_ce12;
high_ad_or[38].ena = ad_ce13;
high_ad_or[44..42].ena = ad_ce13;
high_ad_or[41..39].ena = ad_ce14;
high_ad_or[51].ena = ad_ce14;
high_ad_or[50..47].ena = ad_ce15;
high_ad_or[46].ena = ad_ce16;
high_ad_or[52].ena = ad_ce16;
high_ad_or[58..57].ena = ad_ce16;
high_ad_or[56..53].ena = ad_ce17;
high_ad_or[62..59].ena = ad_ce18;
high_ad_or[63].ena = ad_ce19;
ELSE GENERATE
IF (TARGET_DEVICE == "EPF10K130EFC484") GENERATE
ad_ce_lc = LCELL(not adOR_hi_dena and not m_ador_hi_dena);
ad_ce[19..10] = ((trdy and irdy) or ad_ce_nc) AND ad_ce_lc;
high_ad_or[32].ena = ad_ce10;
high_ad_or[37..36].ena = ad_ce10;
high_ad_or[33].ena = ad_ce11;
high_ad_or[38].ena = ad_ce11;
high_ad_or[42..41].ena = ad_ce11;
high_ad_or[35..34].ena = ad_ce12;
high_ad_or[44].ena = ad_ce12;
high_ad_or[39].ena = ad_ce13;
high_ad_or[49..47].ena = ad_ce13;
high_ad_or[40].ena = ad_ce14;
high_ad_or[43].ena = ad_ce14;
high_ad_or[51..50].ena = ad_ce14;
high_ad_or[45].ena = ad_ce15;
high_ad_or[46].ena = ad_ce16;
high_ad_or[52].ena = ad_ce16;
high_ad_or[58..57].ena = ad_ce16;
high_ad_or[56..53].ena = ad_ce17;
high_ad_or[62..59].ena = ad_ce18;
high_ad_or[63].ena = ad_ce19;
ELSE GENERATE
IF (TARGET_DEVICE == "NEW") GENERATE
ad_ce_lc = LCELL(not adOR_hi_dena and not m_ador_hi_dena);
ad_ce[63..32] = ((trdy and irdy) or ad_ce_nc) AND ad_ce_lc;
-- ad_ce[63..32] = ((trdy and irdy) and (not adOR_hi_dena and not m_ador_hi_dena))
-- OR LCELL((ad_ce_nc) and (not adOR_hi_dena and not m_ador_hi_dena));
high_ad_or[63..32].ena = ad_ce[63..32];
ELSE GENERATE
ad_ce_lc = LCELL(not adOR_hi_dena and not m_ador_hi_dena);
ad_ce[63..32] = ((trdy and irdy) or ad_ce_nc) AND ad_ce_lc;
-- ad_ce[63..32] = ((trdy and irdy) and (not adOR_hi_dena and not m_ador_hi_dena))
-- OR LCELL((ad_ce_nc) and (not adOR_hi_dena and not m_ador_hi_dena));
high_ad_or[63..32].ena = ad_ce[63..32];
END GENERATE;
END GENERATE;
END GENERATE;
END GENERATE;
END GENERATE;
high_cben_or[].clk = clk;
high_cben_or[].clrn = rstn;
high_cben_or[].ena = mstr_cbe_ce;
high_cben_or[] = high_mstr_cbe_out[];
ad_tri_oe = (trg_ad_oe OR mstr_ad_oe);
ad_tri[31..0] = low_ad_OR[]; -- AD Tristate Buffers
ad_tri[63..32] = high_ad_OR[63..32]; -- AD Tristate Buffers
ad_tri[].oe = ad_tri_oe;
ad[] = ad_tri[]; -- AD Output
cbe_tri[3..0] = low_cben_or[]; -- cben Tristate Buffer
cbe_tri[7..4] = high_cben_or[]; -- cben Tristate Buffer
cbe_tri[].oe = mstr_cbe_oe;
cben[] = cbe_tri[]; -- cben Output
--***PCI CONTROL***
-- AD INPUT Bus Signals
ad_IR_ce_data = (trg_ad_IR_ce_D or mstr_ad_IR_ce_D);
ad_IR_ce_address = (trg_ad_IR_ce_A or mstr_ad_ir_ce_a);
ad_IR_address[].clk = clk; -- AD Input Registers
ad_IR_address[].clrn = rstn;
low_ad_IR_data[].clk = clk; -- AD Input Registers
low_ad_IR_data[].clrn = rstn;
high_ad_IR_data[].clk = clk; -- AD Input Registers
high_ad_IR_data[].clrn = rstn;
low_ad_IR_data[].ena = ad_IR_ce_data;
high_ad_IR_data[].ena = ad_IR_ce_data;-- and not trg_cfg_cyc_out;
ad_IR_address[].ena = ad_IR_ce_address;
-- Splitting the address and data bus allows for a target access in case that local side asserts wait states for too
-- long
ad_IR_address[] = ad[31..0]; --Adderss AD input is used to capture the addresses
low_ad_IR_data[] = ad[31..0]; --Data is used to capture data
high_ad_IR_data[] = ad[63..32]; --Data is used to capture data
-- cben Bus Signals
cben_IR_ce_data = (trg_cben_IR_ce_D or mstr_cben_ir_ce_d);
cben_IR_ce_address = (trg_cben_IR_ce_A or mstr_cben_ir_ce_a);
cben_IR_address[].clk = clk; -- cben Input Register
cben_IR_address[].clrn = rstn;
cben_IR_address[].ena = cben_IR_ce_address;
cben_IR_address[] = cben[3..0];
high_cben_IR_data[].clk = clk; -- cben Input Register
high_cben_IR_data[].clrn = rstn;
high_cben_IR_data[].ena = cben_IR_ce_data;-- and not trg_cfg_cyc_out; -- added not cfg_cyc because of "XX" in ModelTech
high_cben_IR_data[] = cben[7..4];
low_cben_IR_data[].clk = clk; -- cben Input Register
low_cben_IR_data[].clrn = rstn;
low_cben_IR_data[].ena = cben_IR_ce_data;
low_cben_IR_data[] = cben[3..0];
--*****************************************************************************
--***************************CONTROL SIGNALS***********************************
--***PCI CONTROL***
-- Frame Signal
frame = NOT framen_in; -- Active High FRAME Input
framen_out = TRI(NOT frame_out, frame_oe); -- framen Output
-- Req64 Signal
req64 = NOT req64n_in; -- Active High FRAME Input
req64n_out = TRI(NOT req64_out, req64_oe); -- framen Output
-- Ack64 Signal
ack64 = NOT ack64n_in; -- Active High FRAME Input
ack64n_out = TRI(NOT ack64_out, targ_oeR); -- framen Output
-- IRDY Signal
irdy = NOT irdyn_in; -- Active High IRDY Input
irdyn_out = TRI(NOT irdy_out, irdy_oe); -- irdyn tristate buffer
-- Devsel Signal
devsel = not devseln_in; -- Active High DEVSEL Input
devseln_out = TRI( NOT devsel_out, targ_oeR); -- devseln Output
-- TRDY Signal
trdy = not trdyn_in; -- Active High trdy Input
trdyn_out = tri(NOT trdy_out, targ_oeR); -- trdyn tristate buffer
-- STOP Signal
stop = not stopn_in; -- Active High stop Input
stopn_out = TRI( NOT stop_out, targ_oeR); -- stopn tristate buffer
-- GNTn signal
gnt = not gntn;
if (INTERNAL_ARBITER == "NO") GENERATE
-- REQn Signal
reqn = TRI(NOT req_out, rstn); -- REQn Output
ELSE GENERATE
-- -- REQn Signal
reqn = NOT req_out; -- REQn Output
END GENERATE;
-- INTAn Signal
inta_or.clk = clk ; -- inta output regsister
inta_or.prn = rstn;
inta_or = lirqn ;
intan = OPNDRN(inta_or); -- intan tristate buffer
-- Internal Signals for Local Signals
lm_req64 = not lm_req64n;
lm_req32 = not lm_req32n;
--IF (DUAL_ADDRESS_ENA == "NO") GENERATE
-- lm_adr64 = gnd;
--ELSE GENERATE
-- lm_adr64 = not lm_adr64n;
--END GENERATE;
lm_adr_ackn = not lm_adr_ack;
lm_last = not lm_lastn;
lm_last = not lm_lastn;
-- IF 64BIT_SYSTEM == "YES" GENERATE
-- 64bit_PCI = VCC;
-- ELSE GENERATE
-- 64bit_PCI = GND;
-- END GENERATE;
stat_reg[5..0] = (perr_det, serr_sig, mabort_rcvd, tabort_rcvd, tabort_sig, perr_rep);
cmd_reg[5..0] = (serr_ena, perr_ena, mwi_ena, mstr_ena, mem_ena, io_ena);
END;