www.pudn.com > s3c2443_test_code.zip > Hspi.h

#ifndef __HSPI_H__ 
#define __HSPI_H__ 
 
#ifdef __cplusplus 
extern "C" { 
#endif 
 
#define HSPI_BYTE			0 
#define HSPI_HWORD			1 
#define HSPI_WORD			2 
 
#define Master 			0 
#define Slave 			1 
 
#define DMAMODE		0 
#define INTMODE			1 
#define POLLMODE		2 
 
#define CPOLHIGH		0 
#define CPOLLOW			1 
#define FORMAT_A		0 
#define FORMAT_B		1 
 
#define HSPI_PCLK		0 
#define HSPI_EPLL		2 
#define HSPI_USBPHY		3 
 
 
#define	CH_SW_RST               (1<<5) 
#define	CH_MASTER               (0<<4) 
#define	CH_SLAVE                (1<<4) 
#define	CH_RISING               (0<<3) 
#define	CH_FALLING              (1<<3) 
#define	CH_FORMAT_A             (0<<2) 
#define	CH_FORMAT_B             (1<<2) 
#define	CH_RXCH_OFF             (0<<1) 
#define	CH_RXCH_ON              (1<<1) 
#define	CH_TXCH_OFF             (0<<0) 
#define	CH_TXCH_ON              (1<<0) 
                              
#define	CLK_CLKSEL_PCLK         (0<<9) 
#define	CLK_CLKSEL_HCLK         (1<<9) 
#define	CLK_CLKSEL_ECLK         (2<<9) 
#define	CLK_CLKSEL_MPLL         (3<<9) 
#define	CLK_ENCLK_DISABLE       (0<<8) 
#define	CLK_ENCLK_ENABLE        (1<<8) 
 
#define	MODE_BUS_SZ_BYTE        (0<<18) 
#define	MODE_BUS_SZ_WORD        (1<<18) 
#define	FEED_BACK_DELAY        (1<<17) 
#define	MODE_BUS_4BURST        (1<<0) 
#define	MODE_BUS_SINGLE        (0<<0) 
#define	BURST       	 			1 
#define	SINGLE       	 			0 
//#define	MODE_SWAP_DISABLE       (0<<3) 
//#define	MODE_SWAP_ENABLE        (1<<3) 
#define	MODE_RXDMA_ON           (1<<2) 
#define	MODE_TXDMA_ON           (1<<1) 
#define	MODE_DMA_SINGLE         0 
#define	MODE_DMA_4BURST         1 
 
#define	INT_TRAILING            (1<<6) 
#define	INT_RX_OVERRUN          (1<<5) 
#define	INT_RX_UNDERRUN         (1<<4) 
#define	INT_TX_OVERRUN          (1<<3) 
#define	INT_TX_UNDERRUN         (1<<2) 
#define	INT_RX_FIFORDY          (1<<1) 
#define	INT_TX_FIFORDY          (1<<0) 
 
#define	STUS_TX_DONE            (1<<21) 
#define	STUS_TRAILCNT_ZERO      (1<<20) 
#define	STUS_RX_OVERRUN         (1<<5) 
#define	STUS_RX_UNDERRUN        (1<<4) 
#define	STUS_TX_OVERRUN         (1<<3) 
#define	STUS_TX_UNDERRUN        (1<<2) 
#define	STUS_RX_FIFORDY         (1<<1) 
#define	STUS_TX_FIFORDY         (1<<0) 
 
enum DMA_HS_MODE 
{ 
	DEMAND, HANDSHAKE 
}; 
 
enum DMA_REQUEST_MODE 
{ 
	SOFTWARE, HARDWARE 
}; 
 
#define LOCAHB	0 
#define LOCAPB	1 
#define ADDRINC	0 
#define ADDRFIX	1 
 
void Test_HSPI(void); 
void Test_Master_INT_FullDuplex(void); 
void Test_Slave_INT_FullDuplex(void); 
void Test_Master_DMA_FullDuplex(void); 
void Test_Slave_DMA_FullDuplex(void); 
 
void Test_MasterTxOnly_INT(void); 
void Test_SlaveRxOnly_INT(void); 
void Test_MasterRxOnly_INT(void); 
void Test_SlaveTxOnly_INT(void); 
void Test_MasterTxOnly_DMA(void); 
void Test_SlaveRxOnly_DMA(void); 
void Test_MasterRxOnly_DMA(void); 
void Test_SlaveTxOnly_DMA(void); 
void InitHSPI(U32 MasterSlave, U32 Cpol, U32 Cpha, U32 ClkSel); 
void TxDMAInit(U32 uSrcAddr, U32 uDstAddr, U32 uDataCnt); 
void RxDMAInit(U32 uSrcAddr, U32 uDstAddr, U32 uDataCnt); 
 
void HS_SPI_ERROR_CHECK(void); 
void CalculationBPS(int Time); 
 
void __irq HSPI_Int(void); 
void __irq HSPI_Int_Byte(void); 
void __irq DmaDone(void); 
void __irq HSPI_Tx_Int(void); 
void __irq HSPI_Rx_Int(void); 
void __irq HSPI_Tx_Int_Byte(void); 
void __irq HSPI_Rx_Int_Byte(void); 
void __irq HSPI_ERR_Int(void); 
void __irq DmaDone_FullDuplex(void); 
void __irq HSPI_Int_Slave(void); 
void __irq HSPI_Int_Master(void); 
 
void CompareData(U32 a0, U32 a1, U32 bytes); 
 
void Reset(void); 
void nSSLow(void); 
void nSSHigh(void); 
void GPIOPortSet(void); 
 
void __irq HSPI_Int_SlaveWord(void); 
void __irq HSPI_Int_MasterWord(void); 
 
#ifdef __cplusplus 
} 
#endif 
 
#endif //__SPI_H__