www.pudn.com > s3c2443_test_code.zip > Option.h

 
#ifndef __OPTION_H__ 
#define __OPTION_H__ 
 
#ifdef __cplusplus 
extern "C" { 
#endif 
 
 
 
#define		SEMIHOSTING	FALSE 
 
#define 	_NONCACHE_STARTADDRESS		0x31000000 
#define 	_RAM_STARTADDRESS			0x30000000 
#define 	_MMUTT_STARTADDRESS			0x33ff8000 
#define 	_ISR_STARTADDRESS			0x33ffff00 
 
 
//===================================================================================== 
//	Fin = 12MHz, 
// 
//	MPLLout = (2m x Fin)/(p x 2**s), m=MDIV+8, p=PDIV, s=SDIV, Fin=10~30MHz 
//	(17,1,1)=300Mhz, (92,3,1)=400Mhz, (67,2,1)=450Mhz, (81,2,1)=534Mhz,  
//	(17,1,0)=600Mhz, (92,3,0)=800Mhz 
// 
//	EPLLout = (m x Fin)/(p x 2**s), m=MDIV+8, p=PDIV+2, s=SDIV, Fin=10~100MHz 
//	(28,1,2)=36Mhz, (40,1,2)=48Mhz, (22,1,1)=60Mhz, (28,1,1)=72Mhz, (34,1,1)=84Mhz 
//	(40,1,1)=96Mhz 
//===================================================================================== 
 
#define		FIN					12000000 
 
#define		Startup_MDIV		92 
#define		Startup_PDIV		3 
#define		Startup_SDIV		1 
 
#define		Startup_ARMCLKdiv	0		//	0	 :	ARMCLK	= MPLL/1 
										//	8	 :	ARMCLK	= MPLL/2 
										//	2	 :	ARMCLK	= MPLL/3 
										//	9	 :	ARMCLK	= MPLL/4 
										//	10	 :	ARMCLK	= MPLL/6 
										//	11	 :	ARMCLK	= MPLL/8 
										//	13	 :	ARMCLK	= MPLL/12 
										//	15	 :	ARMCLK	= MPLL/16 
 
#define		Startup_PREdiv		0x1		//	0x0  :	PREDIV_CLK	= ARMCLK 
										//	0x1 :	PREDIV_CLK	= ARMCLK/2 
										//	0x2 :	PREDIV_CLK	= ARMCLK/3 
										//	0x3 :	PREDIV_CLK	= ARMCLK/4 
																		 
#define		Startup_HCLKdiv		0x1		//	0x0  :	HCLK	= PREDIV_CLK 
										//	0x1 :	HCLK	= PREDIV_CLK/2 
									    //	0x3 :	HCLK	= PREDIV_CLK/4 
 
#define		Startup_PCLKdiv		1		//	0	 :	PCLK	= HCLK 
										//	1	 :	PCLK	= HCLK/2 
 
#define		tREFRESH		780		//	'us' * 100 
 
#define		tRAS			50		//	'ns' 
#define		tRC				73		//	'ns' 
#define		tRCD			23		//	'ns' 
#define		tRP				23		//	'ns' 
 
#define		CL				3 
 
 
#ifdef __cplusplus 
} 
#endif 
 
#endif /*__OPTION_H__*/