www.pudn.com > s3c2443_test_code.zip > MMUCache.h

/***************************************** 
 NAME: MMU.H 
 DESC: MMU Header 
 HISTORY: 
 2003.04.04 : ver 0.0 
******************************************/ 
 
#ifndef __MMUCACHE_H__ 
#define __MMUCACHE_H__ 
 
#ifdef __cplusplus 
extern "C" { 
#endif 
 
#define DESC_SEC	((1<<1)|(1<<4)) 
#define CB			(3<<2)  //cache_on, write_back 
#define CNB			(2<<2)  //cache_on, write_through  
#define NCB         (1<<2)  //cache_off,WR_BUF on 
#define NCNB		(0<<2)  //cache_off,WR_BUF off 
#define AP_RW		(3<<10) //supervisor=RW, user=RW 
#define AP_RO		(2<<10) //supervisor=RW, user=RO 
#define AP_NO		(1<<10) //supervisor=RW, user=No access 
 
#define DOMAIN_FAULT	(0x0) 
#define DOMAIN_CHK		(0x1)  
#define DOMAIN_NOTCHK	(0x3)  
#define DOMAIN0			(0x0<<5) 
#define DOMAIN1			(0x1<<5) 
 
#define DOMAIN0_ATTR	(DOMAIN_CHK<<0)  
#define DOMAIN1_ATTR	(DOMAIN_FAULT<<2)  
 
#define RW_CB		(AP_RW|DOMAIN0|CB|DESC_SEC) 
#define RW_CNB		(AP_RW|DOMAIN0|CNB|DESC_SEC) 
#define RW_NCB		(AP_RW|DOMAIN0|NCB|DESC_SEC) 
#define RW_NCNB		(AP_RW|DOMAIN0|NCNB|DESC_SEC) 
#define RW_FAULT	(AP_RW|DOMAIN1|NCNB|DESC_SEC) 
 
//------------------------------ 
// in MMUCache_asm.s 
//------------------------------ 
// CPSR I,F bit 
int SET_IF(void); 
void WR_IF(int cpsrValue); 
void CLR_IF(void); 
// MMU Cache/TLB/etc on/off functions 
void MMU_EnableICache(void); 
void MMU_DisableICache(void); 
void MMU_EnableDCache(void); 
void MMU_DisableDCache(void); 
void MMU_EnableAlignFault(void); 
void MMU_DisableAlignFault(void); 
void MMU_EnableMMU(void); 
void MMU_DisableMMU(void); 
void MMU_SetFastBusMode(void); 
void MMU_SetAsyncBusMode(void); 
// Set TTBase 
void MMU_SetTTBase(int base); 
// Set Domain 
void MMU_SetDomain(int domain); 
// Read Fault Status & Address 
int MMU_ReadDFSR(void); 
int MMU_ReadIFSR(void); 
int MMU_ReadFAR(void); 
// ICache/DCache functions 
void MMU_InvalidateIDCache(void); 
void MMU_InvalidateICache(void); 
void MMU_InvalidateICacheMVA(U32 mva); 
void MMU_PrefetchICacheMVA(U32 mva); 
void MMU_InvalidateDCache(void); 
void MMU_InvalidateDCacheMVA(U32 mva); 
void MMU_CleanDCacheMVA(U32 mva); 
void MMU_CleanInvalidateDCacheMVA(U32 mva); 
void MMU_CleanDCacheIndex(U32 index); 
void MMU_CleanInvalidateDCacheIndex(U32 index); 
void MMU_WaitForInterrupt(void); 
// TLB functions 
void MMU_InvalidateTLB(void); 
void MMU_InvalidateITLB(void); 
void MMU_InvalidateITLBMVA(U32 mva); 
void MMU_InvalidateDTLB(void); 
void MMU_InvalidateDTLBMVA(U32 mva); 
// Cache lock down 
void MMU_SetDCacheLockdownBase(U32 base); 
void MMU_SetICacheLockdownBase(U32 base); 
// TLB lock down 
void MMU_SetDTLBLockdown(U32 baseVictim); 
void MMU_SetITLBLockdown(U32 baseVictim); 
// Process ID 
void MMU_SetProcessId(U32 pid); 
 
//------------------------------ 
// in MMUCache.c 
//------------------------------ 
void MMU_Init(void); 
void MMU_SetMTT(unsigned int vaddrStart,unsigned int vaddrEnd,unsigned int paddrStart,unsigned int attr); 
void ChangeRomCacheStatus(int attr); 
 
#ifdef __cplusplus 
} 
#endif 
 
#endif /*__MMUCACHE_H__*/