www.pudn.com > ASM86_64.rar > i_attribute.h
#ifndef i_attribute_H_
#define i_attribute_H_
/*
* i_attribute.h
*
* the header file define instruction attribute for X86-64 instruction set
*
* author: Mik
*
* e-mail: mikdeng@163.com
*
* 11/12/2005
*/
typedef struct GPI {
unsigned int i_attr;
unsigned short opcode;
} gpi_t;
typedef struct GPI1 {
unsigned int so_attr;
unsigned int i_attr;
unsigned short opcode;
} gpi1_t;
typedef struct GPI2 {
unsigned int do_attr;
unsigned int so_attr;
unsigned int i_attr;
unsigned short opcode;
} gpi2_t;
typedef struct GPI3 {
unsigned int to_attr;
unsigned int do_attr;
unsigned int so_attr;
unsigned int i_attr;
unsigned short opcode;
} gpi3_t, i_key_t;
typedef struct X87 {
} x87_t;
typedef struct MMX {
} mmx_t;
typedef struct XMM {
} xmm_t;
typedef struct _3DNOW {
} _3dnow_t;
typedef struct {
char *mnemonic; /* instruction menmonic */
void *i_key; /* key word array for echo instruction */
} i_set_t; /* X86-64 instructon set */
/*******************************************************
***** operand attribute key word *******
0000 0000 0000 0000 0000 0000 0000 0000
---- ---- ---- ---- ---- ---- ---- ----
|||| |||| |||| || || | | ||||
++++-++++-++++-++---++---+-------+-++++----> 31-bit: rAX register
||| |||| |||| || || | | ||||
+++-++++-++++-++---++---+-------+-++++----> 30-bit: rCX register
|| |||| |||| || || | | ||||
++-++++-++++-++---++---+-------+-++++----> 29-bit: rDX register
| |||| |||| || || | | ||||
+-++++-++++-++---++---+-------+-++++----> 28-bit: rBX register
|||| |||| || || | | ||||
++++-++++-++---++---+-------+-++++----> 27-bit: rSP register
||| |||| || || | | ||||
+++-++++-++---++---+-------+-++++----> 26-bit: rBP register
|| |||| || || | | ||||
++-++++-++---++---+-------+-++++----> 25-bit: rSI register
| |||| || || | | ||||
+-++++-++---++---+-------+-++++----> 24-bit: rDI register
|||| || || | | ||||
++++-++---++---+-------+-++++----> 23-bit: GPR
||| || || | | ||||
+++-++---++---+-------+-++++----> 22-bit: MMX
|| || || | | ||||
++-++---++---+-------+-++++----> 21-bit: XMM
| || || | | ||||
+-++---++---+-------+-++++----> 20-bit: segment register
|| || | | ||||
++---++---+-------+-++++----> 19-bit: control register
| || | | ||||
+---++---+-------+-++++----> 18-bit: debug register
|| | | ||||
++---+-------+-++++----> 15-bit: MEM bit
| | | ||||
+---+-------+-++++----> 14-bit: MOFFSET bit
| | ||||
+-------+-++++----> 11-bit: IMME bit
| ||||
+-++++----> 4-bit: SIZE128
||||
++++----> 3-bit: SIZE64
|||
+++----> 2-bit: SIZE32
||
++----> 1-bit: SIZE16
|
+----> 0-bit: SIZE8
********************************************************/
/* o_attr.reg field */
#define GPR 0x800000
#define MMX 0x400000
#define XMM 0x200000
#define SREG 0x100000
#define CREG 0x080000
#define DREG 0x040000
/* o_attr.mem field */
#define MEM 0x8000
#define MOFFSET 0x4000
#define FAR_POINTER 0x2000
/* o_attr.imme field */
/* #define IMME 0x800 */
#define IMME 0xc00
#define IMME_1 0x400
/* o_attr.size field */
#define SIZE8 0x1
#define SIZE16 0x2
#define SIZE32 0x4
#define SIZE64 0x8
#define SIZE128 0x10
#define SIZE_V 0x0e
/*
* register IDs
*
* rAX include: AL/AX/EAX/RAX/MMX0/XMM0/ES/CR0/DR0
* .......
*/
#define rAX 0x80000000
#define rCX 0x40000000
#define rDX 0x20000000
#define rBX 0x10000000
#define rSP 0x08000000
#define rBP 0x04000000
#define rSI 0x02000000
#define rDI 0x01000000
#define ALL_REGS 0xff000000
#define REGID(x) ((x) & 0xff000000)
#define OPTYPE(x) ((x) & 0x00ffff00)
#define SIZE(x) ((x) & 0x000000ff)
/*************************************************************
instruction attribute key word (32bit):
000 0 000 0 000 0 0000 0 000 0000 0000 0000
--- - --- - --- - ---- - --- ---- ---- ----
| | | | | || | |
+-------+--+---+--+-++----+--+--------------------> 31-29: instruction types
| | | | || | |
+--+---+--+-++----+--+--------------------> 27-26: operand fixed size
| | | || | |
| +--+-++----------------------------> 25-24: operand default size
| | || | |
| | ++----+--+--------------------> 23: invalid in 64-bit mode
| | | | |
V | +----+--+--------------------> 22: cannot promoted 64-bit
| | |
FS_IN_BITS | +--+--------------------> 18: group bit
| |
V +--------------------> 17-15: group IDs
DEST_EXTEND
**************************************************************/
#define I_GPI 0x0
#define I_X87 0x20000000
#define I_MMX 0x40000000
#define I_XMM 0x60000000
#define I_3DNOW 0x80000000
#define INS_TYPE(x) ((x) & 0xe0000000)
/* i_attr.fixed size field */
#define FS_8 0x2000000
#define FS_16 0x4000000
#define FS_32 0x6000000
#define FS_64 0x8000000
#define get_FS(x) ((x) & 0xE000000)
#define get_FS_SIZE(x) \
is_FS_8(x) ? 8 : is_FS_16(x) ? 16 : is_FS_32(x) ? 32 : is_FS(x) ? 64 : 0;
#define is_FS(x) ((x) & 0xe000000)
#define is_FS_64(x) (get_FS(x) == FS_64)
#define is_FS_32(x) (get_FS(x) == FS_32)
#define is_FS_16(x) (get_FS(x) == FS_16)
#define is_FS_8(x) (get_FS(x) == FS_8)
#define FS_IN_BITS 0x01000000
#define is_FS_IN_BITS(x) ((x) & FS_IN_BITS)
/* i_attr.default size field */
#define DS_8 0x200000
#define DS_16 0x400000
#define DS_32 0x600000
#define DS_64 0x800000
#define get_DS(x) ((x) & 0xE00000)
#define is_DS_8(x) (get_DS(x) == DS_8)
#define is_DS_16(x) (get_DS(x) == DS_16)
#define is_DS_32(X) (get_DS(x) == DS_32)
#define is_DS_64(x) (get_DS(x) == DS_64)
#define DEST_EXTEND 0x100000
#define is_DEST_EXTEND(x) ((x) & DEST_EXTEND)
/* i_attr.INVALID_IN_64 field */
#define INVLD_IN_64 0x80000
#define is_INVLD_IN_64(x) ((x) & INVLD_IN_64)
/* i_attr.not promoted to 64 field */
#define CANNOT_64 0x40000
#define is_CANNOT_64(x) ((x) & CANNOT_64)
#define ONLY_IN_16 0x10000
#define ONLY_IN_32 0x20000
#define ONLY_IN_64 0x30000
#define is_ONLY_IN_BITS(x) ((x) & 0x30000)
#define is_ONLY_IN_16(x) (((x) & 0x30000) == ONLY_IN_16)
#define is_ONLY_IN_32(x) (((x) & 0x30000) == ONLY_IN_32)
#define is_ONLY_IN_64(x) (((x) & 0x30000) == ONLY_IN_64)
#define get_ONLY_BITS(x) \
(is_ONLY_IN_16(x) ? 16 : is_ONLY_IN_32(x) ? 32 : 64)
#define get_INS(x) ((x) & 0xE0000000)
#define is_X87(x) (get_INS(x) == X87_INS)
#define is_3DNow(x) (get_INS(x) == 3DNow_INS)
#define is_XMM(x) (get_INS(x) == XMM_INS)
/* i_attr.group field */
#define GROUP 0x8000
#define GROUPID(x) ((x) << 12)
#define is_GROUP(x) ((x) & GROUP)
#define get_GROUPID(x) (((x) & 0x7000) >> 9)
/* i_attr.rip-relative address field */
#define PC_RELATIVE 0x8
#define is_PC_RELATIVE(x) ((x) & RIP_RELATIVE)
// #define FAR_POINTER 0x4
/* i_attr.only-opcode filed */
/* example: "inc eax" is only opcode without modrm byte */
#define ONLY_OPCODE 0x2
#define is_ONLY_OPCODE(x) ((x) & ONLY_OPCODE)
/* i_attr.need-modrm field */
/*
* becase a few instruction's modrm in opcode reg field
* example: inc eax,
* dec eax. so that......
*
* there have not modrm byte !!!
*/
#define NO_NEED_MODRM 0x1
#define is_NO_NEED_MODRM(x) ((x) & NO_NEED_MODRM)
/* NO_CASE: the mean is instuction fix operand size in all bit mode */
/* example: "push cs", so that ...... */
#define NO_CAST 0x30
#define is_NO_CAST(x) (((x) & 0x30) == NO_CAST)
#define NO_CAST_SIZE 0x10
#define is_NO_CAST_SIZE(x) (((x) & 0x30) == NO_CAST_SIZE)
#define NO_CAST_ADDR 0x20
#define is_NO_CAST_ADDR(x) (((x) & 0x30) == NO_CAST_ADDR)
#define SUPPORT_VALUE64 0x40
#define is_SUPPORT_VALUE64(x) ((x) & SUPPORT_VALUE64)
#endif