www.pudn.com > dvi_demo.rar > synchro.v, change:2008-07-24,size:3890b


////////////////////////////////////////////////////////////////////////////// 
// Copyright (c) 2006 Xilinx, Inc. 
// This design is confidential and proprietary of Xilinx, All Rights Reserved. 
////////////////////////////////////////////////////////////////////////////// 
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /   Vendor:        Xilinx 
// \   \   \/    Version:       1.0.0 
//  \   \        Filename:      synchro.v 
//  /   /        Date Created:  December 25, 2006 
// /___/   /\    Last Modified: December 25, 2006 
// \   \  /  \ 
//  \___\/\___\ 
// 
// Devices:   Spartan-3 Generation FPGA 
// Purpose:   Signal synchronizer, for async inputs 
// Contact:   crabill@xilinx.com 
// Reference: None 
// 
// Revision History: 
//   Rev 1.0.0 - (crabill) First created December 25, 2006. 
// 
////////////////////////////////////////////////////////////////////////////// 
// 
// LIMITED WARRANTY AND DISCLAIMER. These designs are provided to you "as is". 
// Xilinx and its licensors make and you receive no warranties or conditions, 
// express, implied, statutory or otherwise, and Xilinx specifically disclaims 
// any implied warranties of merchantability, non-infringement, or fitness for 
// a particular purpose. Xilinx does not warrant that the functions contained 
// in these designs will meet your requirements, or that the operation of 
// these designs will be uninterrupted or error free, or that defects in the 
// designs will be corrected. Furthermore, Xilinx does not warrant or make any 
// representations regarding use or the results of the use of the designs in 
// terms of correctness, accuracy, reliability, or otherwise. 
// 
// LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be liable 
// for any loss of data, lost profits, cost or procurement of substitute goods 
// or services, or for any special, incidental, consequential, or indirect 
// damages arising from the use or operation of the designs or accompanying 
// documentation, however caused and on any theory of liability. This 
// limitation will apply even if Xilinx has been advised of the possibility 
// of such damage. This limitation shall apply not-withstanding the failure 
// of the essential purpose of any limited remedies herein. 
// 
////////////////////////////////////////////////////////////////////////////// 
// Copyright (c) 2006 Xilinx, Inc. 
// This design is confidential and proprietary of Xilinx, All Rights Reserved. 
////////////////////////////////////////////////////////////////////////////// 
 
`timescale 1 ns / 1 ps 
 
module synchro 
  #( 
  parameter          INITIALIZE = "LOGIC0" 
  ) 
 
  ( 
  input  wire        async, 
  input  wire        clk, 
  output wire        sync 
  ); 
 
  //******************************************************************// 
  // Synchronizer.                                                    // 
  //******************************************************************// 
 
  wire        temp; 
 
  generate 
    if (INITIALIZE == "LOGIC1") 
    begin : use_fdp 
      FDP fda (.Q(temp),.D(async),.C(clk),.PRE(1'b0)); 
      FDP fdb (.Q(sync),.D(temp),.C(clk),.PRE(1'b0)); 
    end 
    else 
    begin : use_fdc 
      FDC fda (.Q(temp),.D(async),.C(clk),.CLR(1'b0)); 
      FDC fdb (.Q(sync),.D(temp),.C(clk),.CLR(1'b0)); 
    end 
  endgenerate 
 
  // synthesis attribute ASYNC_REG of fda is "TRUE"; 
  // synthesis attribute ASYNC_REG of fdb is "TRUE"; 
  // synthesis attribute HU_SET of fda is "SYNC"; 
  // synthesis attribute HU_SET of fdb is "SYNC"; 
  // synthesis attribute RLOC of fda is "X0Y0"; 
  // synthesis attribute RLOC of fdb is "X0Y0"; 
 
  //******************************************************************// 
  //                                                                  // 
  //******************************************************************// 
 
endmodule