www.pudn.com > brent_kung_add.rar > csla_tb.v, change:2016-04-04,size:1156b


`timescale 1ns / 1ps 
 
//////////////////////////////////////////////////////////////////////////////// 
// Company:  
// Engineer: 
// 
// Create Date:   14:34:35 04/04/2016 
// Design Name:   carry_select 
// Module Name:   C:/Users/hai/Desktop/brent_kung_add/csla_tb.v 
// Project Name:  brent_kung_add 
// Target Device:   
// Tool versions:   
// Description:  
// 
// Verilog Test Fixture created by ISE for module: carry_select 
// 
// Dependencies: 
//  
// Revision: 
// Revision 0.01 - File Created 
// Additional Comments: 
//  
//////////////////////////////////////////////////////////////////////////////// 
 
module csla_tb; 
 
	// Inputs 
	reg [15:0] a; 
	reg [15:0] b; 
	reg cin; 
 
	// Outputs 
	wire [15:0] sum; 
	wire co; 
 
	// Instantiate the Unit Under Test (UUT) 
	carry_select uut ( 
		.a(a),  
		.b(b),  
		.cin(cin),  
		.sum(sum),  
		.co(co) 
	); 
 
	initial begin 
		// Initialize Inputs 
		a = 0; 
		b = 0; 
		cin = 0; 
 
		// Wait 100 ns for global reset to finish 
		#100; 
         
		// Add stimulus here 
		 
		a="0000000000000011"; 
		b="0000000000000111"; 
		cin="0000000000000000"; 
		 
 
	end 
       
endmodule