www.pudn.com > brent_kung_add.rar > bkppa_test.v, change:2015-06-27,size:1187b


`timescale 1ns / 1ps 
 
 
//////////////////////////////////////////////////////////////////////////////// 
// Company:  
// Engineer: 
// 
// Create Date:   10:15:27 06/27/2015 
// Design Name:   bkppa 
// Module Name:   E:/ravi's/ravi codes/brent_kung_add/bkppa_test.v 
// Project Name:  brent_kung_add 
// Target Device:   
// Tool versions:   
// Description:  
// 
// Verilog Test Fixture created by ISE for module: bkppa 
// 
// Dependencies: 
//  
// Revision: 
// Revision 0.01 - File Created 
// Additional Comments: 
//  
//////////////////////////////////////////////////////////////////////////////// 
 
`include "data.v" 
 
 
module bkppa_test; 
 
 integer k; 
  
 reg[7:0]mem[0:5]; 
  
	// Inputs 
	reg [7:0] x; 
	reg [7:0] y; 
	reg c; 
 
	// Outputs 
	wire [7:0] s; 
 
	// Instantiate the Unit Under Test (UUT) 
	bkppa uut ( 
		.x(x),  
		.y(y),  
		.c(c),  
		.s(s) 
	); 
 
	initial 
	 begin 
		// Initialize Inputs 
		x = 0; 
		y = 0; 
		c = 0; 
    end 
	  
	initial 
	 
	 begin 
	  
	  #10  
	   
       for (k=0;k<5;k=k+1) 
		   
		  begin 
 
        x[k] = mem [k]; 
		   
		  y[k] = mem [k]; 
	     
		  $display ("%b",s); 
		   
		 end 
	end 
       
endmodule