www.pudn.com > 1602_FPGA.rar > decode_ala.tdf, change:2015-12-25,size:3296b


--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_DECODES=5 LPM_WIDTH=3 data enable eq 
--VERSION_BEGIN 13.1 cbx_cycloneii 2013:10:23:18:05:48:SJ cbx_lpm_add_sub 2013:10:23:18:05:48:SJ cbx_lpm_compare 2013:10:23:18:05:48:SJ cbx_lpm_decode 2013:10:23:18:05:48:SJ cbx_mgl 2013:10:23:18:06:54:SJ cbx_stratix 2013:10:23:18:05:48:SJ cbx_stratixii 2013:10:23:18:05:48:SJ  VERSION_END 
 
 
-- Copyright (C) 1991-2013 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files from any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
 
--synthesis_resources = lut 8  
SUBDESIGN decode_ala 
(  
	data[2..0]	:	input; 
	enable	:	input; 
	eq[4..0]	:	output; 
)  
VARIABLE  
	data_wire[2..0]	: WIRE; 
	enable_wire	: WIRE; 
	eq_node[4..0]	: WIRE; 
	eq_wire[7..0]	: WIRE; 
	w_anode1333w[3..0]	: WIRE; 
	w_anode1350w[3..0]	: WIRE; 
	w_anode1360w[3..0]	: WIRE; 
	w_anode1370w[3..0]	: WIRE; 
	w_anode1380w[3..0]	: WIRE; 
	w_anode1390w[3..0]	: WIRE; 
	w_anode1400w[3..0]	: WIRE; 
	w_anode1410w[3..0]	: WIRE; 
 
BEGIN  
	data_wire[] = data[]; 
	enable_wire = enable; 
	eq[] = eq_node[]; 
	eq_node[4..0] = eq_wire[4..0]; 
	eq_wire[] = ( w_anode1410w[3..3], w_anode1400w[3..3], w_anode1390w[3..3], w_anode1380w[3..3], w_anode1370w[3..3], w_anode1360w[3..3], w_anode1350w[3..3], w_anode1333w[3..3]); 
	w_anode1333w[] = ( (w_anode1333w[2..2] & (! data_wire[2..2])), (w_anode1333w[1..1] & (! data_wire[1..1])), (w_anode1333w[0..0] & (! data_wire[0..0])), enable_wire); 
	w_anode1350w[] = ( (w_anode1350w[2..2] & (! data_wire[2..2])), (w_anode1350w[1..1] & (! data_wire[1..1])), (w_anode1350w[0..0] & data_wire[0..0]), enable_wire); 
	w_anode1360w[] = ( (w_anode1360w[2..2] & (! data_wire[2..2])), (w_anode1360w[1..1] & data_wire[1..1]), (w_anode1360w[0..0] & (! data_wire[0..0])), enable_wire); 
	w_anode1370w[] = ( (w_anode1370w[2..2] & (! data_wire[2..2])), (w_anode1370w[1..1] & data_wire[1..1]), (w_anode1370w[0..0] & data_wire[0..0]), enable_wire); 
	w_anode1380w[] = ( (w_anode1380w[2..2] & data_wire[2..2]), (w_anode1380w[1..1] & (! data_wire[1..1])), (w_anode1380w[0..0] & (! data_wire[0..0])), enable_wire); 
	w_anode1390w[] = ( (w_anode1390w[2..2] & data_wire[2..2]), (w_anode1390w[1..1] & (! data_wire[1..1])), (w_anode1390w[0..0] & data_wire[0..0]), enable_wire); 
	w_anode1400w[] = ( (w_anode1400w[2..2] & data_wire[2..2]), (w_anode1400w[1..1] & data_wire[1..1]), (w_anode1400w[0..0] & (! data_wire[0..0])), enable_wire); 
	w_anode1410w[] = ( (w_anode1410w[2..2] & data_wire[2..2]), (w_anode1410w[1..1] & data_wire[1..1]), (w_anode1410w[0..0] & data_wire[0..0]), enable_wire); 
END; 
--VALID FILE