www.pudn.com > 05_key_test.rar > vtf_cnkey_test.v, change:2016-01-29,size:929b


`timescale 1ns / 1ps 
 
//////////////////////////////////////////////////////////////////////////////// 
// Company:  
// Engineer: 
// 
// Create Date:   21:32:47 01/29/2016 
// Design Name:   cnkey_test 
// Module Name:   D:/BaiduYunDownload/FPGA_doc/AX309/09_VERILOG/05_key_test/vtf_cnkey_test.v 
// Project Name:  key_test 
// Target Device:   
// Tool versions:   
// Description:  
// 
// Verilog Test Fixture created by ISE for module: cnkey_test 
// 
// Dependencies: 
//  
// Revision: 
// Revision 0.01 - File Created 
// Additional Comments: 
//  
//////////////////////////////////////////////////////////////////////////////// 
 
module vtf_cnkey_test; 
 
	// Outputs 
	wire ; 
 
	// Instantiate the Unit Under Test (UUT) 
	cnkey_test uut ( 
		.() 
	); 
 
	initial begin 
		// Initialize Inputs 
 
		// Wait 100 ns for global reset to finish 
		#100; 
         
		// Add stimulus here 
 
	end 
       
endmodule