www.pudn.com > 05_key_test.rar > key_test_summary.html, change:2016-01-29,size:14636b


<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>key_test Project Status (01/29/2016 - 19:44:33)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>key_test.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>key_test</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>Synthesized</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx9-2ftg256</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>
No Errors</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT>No Warnings</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
 </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD> </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
<A HREF_DISABLED='D:/BaiduYunDownload/FPGA_doc/AX309/09_VERILOG/05_key_test\key_test_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>  </TD>
</TR>
</TABLE>



 <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>11,440</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>32</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Latches</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Latch-thrus</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as AND/OR logics</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>54</TD>
<TD ALIGN=RIGHT>5,720</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as logic</TD>
<TD ALIGN=RIGHT>53</TD>
<TD ALIGN=RIGHT>5,720</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number using O6 output only</TD>
<TD ALIGN=RIGHT>34</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number using O5 output only</TD>
<TD ALIGN=RIGHT>18</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number using O5 and O6</TD>
<TD ALIGN=RIGHT>1</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number used as ROM</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as Memory</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1,440</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used exclusively as route-thrus</TD>
<TD ALIGN=RIGHT>1</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number with same-slice register load</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number with same-slice carry load</TD>
<TD ALIGN=RIGHT>1</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>        Number with other load</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>1,430</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MUXCYs used</TD>
<TD ALIGN=RIGHT>20</TD>
<TD ALIGN=RIGHT>2,860</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>58</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>26</TD>
<TD ALIGN=RIGHT>58</TD>
<TD ALIGN=RIGHT>44%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number with an unused LUT</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>58</TD>
<TD ALIGN=RIGHT>6%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>28</TD>
<TD ALIGN=RIGHT>58</TD>
<TD ALIGN=RIGHT>48%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number of unique control sets</TD>
<TD ALIGN=RIGHT>3</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number of slice register sites lost<BR>        to control set restrictions</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>11,440</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='D:/BaiduYunDownload/FPGA_doc/AX309/09_VERILOG/05_key_test\key_test_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>10</TD>
<TD ALIGN=RIGHT>186</TD>
<TD ALIGN=RIGHT>5%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number of LOCed IOBs</TD>
<TD ALIGN=RIGHT>10</TD>
<TD ALIGN=RIGHT>10</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>64</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>6%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as BUFGs</TD>
<TD ALIGN=RIGHT>1</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>    Number used as BUFGMUX</TD>
<TD ALIGN=RIGHT>0</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>200</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>200</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>200</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>128</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'> </TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>3.57</TD>
<TD> </TD>
<TD> </TD>
<TD COLSPAN='2'> </TD>
</TR>
</TABLE>







 <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/BaiduYunDownload/FPGA_doc/AX309/09_VERILOG/05_key_test\key_test.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>周一 九月 28 23:31:13 2015</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/BaiduYunDownload/FPGA_doc/AX309/09_VERILOG/05_key_test\key_test.bld'>Translation Report</A></TD><TD>Out of Date</TD><TD>周一 九月 28 23:31:08 2015</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/BaiduYunDownload/FPGA_doc/AX309/09_VERILOG/05_key_test\key_test_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>周一 九月 28 23:31:19 2015</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='D:/BaiduYunDownload/FPGA_doc/AX309/09_VERILOG/05_key_test\_xmsgs/map.xmsgs?&DataKey=Info'>6 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/BaiduYunDownload/FPGA_doc/AX309/09_VERILOG/05_key_test\key_test.par'>Place and Route Report</A></TD><TD>Out of Date</TD><TD>周一 九月 28 23:31:12 2015</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/BaiduYunDownload/FPGA_doc/AX309/09_VERILOG/05_key_test\key_test.twr'>Post-PAR Static Timing Report</A></TD><TD>Out of Date</TD><TD>周一 九月 28 23:31:13 2015</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='D:/BaiduYunDownload/FPGA_doc/AX309/09_VERILOG/05_key_test\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/BaiduYunDownload/FPGA_doc/AX309/09_VERILOG/05_key_test\key_test.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>周五 一月 29 19:44:26 2016</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
 <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/BaiduYunDownload/FPGA_doc/AX309/09_VERILOG/05_key_test\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>周五 一月 29 19:44:27 2016</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='D:/BaiduYunDownload/FPGA_doc/AX309/09_VERILOG/05_key_test\webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>周五 一月 29 19:44:33 2016</TD></TR>
</TABLE>


<br><center><b>Date Generated:</b> 01/29/2016 -