www.pudn.com > 05_key_test.rar > key_test.twr, change:2015-09-28,size:29789b


-------------------------------------------------------------------------------- 
Release 14.7 Trace  (nt64) 
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. 
 
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2 
-n 3 -fastpaths -xml key_test.twx key_test.ncd -o key_test.twr key_test.pcf 
-ucf key_test.ucf 
 
Design file:              key_test.ncd 
Physical constraint file: key_test.pcf 
Device,package,speed:     xc6slx9,ftg256,C,-2 (PRODUCTION 1.23 2013-10-13) 
Report level:             verbose report 
 
Environment Variable      Effect  
--------------------      ------  
NONE                      No environment variables were set 
-------------------------------------------------------------------------------- 
 
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths  
   option. All paths that are not constrained will be reported in the  
   unconstrained paths section(s) of the report. 
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on  
   a 50 Ohm transmission line loading model.  For the details of this model,  
   and for more information on accounting for different loading conditions,  
   please see the device datasheet. 
 
================================================================================ 
Timing constraint: TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_pin" 50 MHz HIGH  
50%; 
For more information, see Period Analysis in the Timing Closure User Guide (UG612). 
 
 710 paths analyzed, 148 endpoints analyzed, 0 failing endpoints 
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) 
 Minimum period is   3.881ns. 
-------------------------------------------------------------------------------- 
 
Paths for end point key_scan_2 (SLICE_X2Y29.D1), 14 paths 
-------------------------------------------------------------------------------- 
Slack (setup path):     16.119ns (requirement - (data path - clock path skew + uncertainty)) 
  Source:               count_2 (FF) 
  Destination:          key_scan_2 (FF) 
  Requirement:          20.000ns 
  Data Path Delay:      3.837ns (Levels of Logic = 3) 
  Clock Path Skew:      -0.009ns (0.339 - 0.348) 
  Source Clock:         clk_BUFGP rising at 0.000ns 
  Destination Clock:    clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.035ns 
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
    Total System Jitter (TSJ):  0.070ns 
    Total Input Jitter (TIJ):   0.000ns 
    Discrete Jitter (DJ):       0.000ns 
    Phase Error (PE):           0.000ns 
 
  Maximum Data Path at Slow Process Corner: count_2 to key_scan_2 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X7Y29.DQ       Tcko                  0.430   count<2> 
                                                       count_2 
    SLICE_X4Y29.D5       net (fanout=3)        1.043   count<2> 
    SLICE_X4Y29.D        Tilo                  0.254   count<19> 
                                                       count[19]_PWR_1_o_equal_1_o<19>2_1 
    SLICE_X2Y29.B1       net (fanout=1)        0.959   count[19]_PWR_1_o_equal_1_o<19>21 
    SLICE_X2Y29.B        Tilo                  0.235   key_scan<2> 
                                                       count[19]_PWR_1_o_equal_1_o<19>4_rstpot 
    SLICE_X2Y29.D1       net (fanout=4)        0.567   count[19]_PWR_1_o_equal_1_o<19>4_rstpot 
    SLICE_X2Y29.CLK      Tas                   0.349   key_scan<2> 
                                                       key_scan_2_dpot1 
                                                       key_scan_2 
    -------------------------------------------------  --------------------------- 
    Total                                      3.837ns (1.268ns logic, 2.569ns route) 
                                                       (33.0% logic, 67.0% route) 
 
-------------------------------------------------------------------------------- 
Slack (setup path):     16.124ns (requirement - (data path - clock path skew + uncertainty)) 
  Source:               count_3 (FF) 
  Destination:          key_scan_2 (FF) 
  Requirement:          20.000ns 
  Data Path Delay:      3.836ns (Levels of Logic = 3) 
  Clock Path Skew:      -0.005ns (0.339 - 0.344) 
  Source Clock:         clk_BUFGP rising at 0.000ns 
  Destination Clock:    clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.035ns 
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
    Total System Jitter (TSJ):  0.070ns 
    Total Input Jitter (TIJ):   0.000ns 
    Discrete Jitter (DJ):       0.000ns 
    Phase Error (PE):           0.000ns 
 
  Maximum Data Path at Slow Process Corner: count_3 to key_scan_2 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X7Y27.AQ       Tcko                  0.430   count<6> 
                                                       count_3 
    SLICE_X4Y29.D2       net (fanout=3)        1.042   count<3> 
    SLICE_X4Y29.D        Tilo                  0.254   count<19> 
                                                       count[19]_PWR_1_o_equal_1_o<19>2_1 
    SLICE_X2Y29.B1       net (fanout=1)        0.959   count[19]_PWR_1_o_equal_1_o<19>21 
    SLICE_X2Y29.B        Tilo                  0.235   key_scan<2> 
                                                       count[19]_PWR_1_o_equal_1_o<19>4_rstpot 
    SLICE_X2Y29.D1       net (fanout=4)        0.567   count[19]_PWR_1_o_equal_1_o<19>4_rstpot 
    SLICE_X2Y29.CLK      Tas                   0.349   key_scan<2> 
                                                       key_scan_2_dpot1 
                                                       key_scan_2 
    -------------------------------------------------  --------------------------- 
    Total                                      3.836ns (1.268ns logic, 2.568ns route) 
                                                       (33.1% logic, 66.9% route) 
 
-------------------------------------------------------------------------------- 
Slack (setup path):     16.154ns (requirement - (data path - clock path skew + uncertainty)) 
  Source:               count_0 (FF) 
  Destination:          key_scan_2 (FF) 
  Requirement:          20.000ns 
  Data Path Delay:      3.802ns (Levels of Logic = 3) 
  Clock Path Skew:      -0.009ns (0.339 - 0.348) 
  Source Clock:         clk_BUFGP rising at 0.000ns 
  Destination Clock:    clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.035ns 
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
    Total System Jitter (TSJ):  0.070ns 
    Total Input Jitter (TIJ):   0.000ns 
    Discrete Jitter (DJ):       0.000ns 
    Phase Error (PE):           0.000ns 
 
  Maximum Data Path at Slow Process Corner: count_0 to key_scan_2 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X7Y29.AQ       Tcko                  0.430   count<2> 
                                                       count_0 
    SLICE_X4Y29.D1       net (fanout=3)        1.008   count<0> 
    SLICE_X4Y29.D        Tilo                  0.254   count<19> 
                                                       count[19]_PWR_1_o_equal_1_o<19>2_1 
    SLICE_X2Y29.B1       net (fanout=1)        0.959   count[19]_PWR_1_o_equal_1_o<19>21 
    SLICE_X2Y29.B        Tilo                  0.235   key_scan<2> 
                                                       count[19]_PWR_1_o_equal_1_o<19>4_rstpot 
    SLICE_X2Y29.D1       net (fanout=4)        0.567   count[19]_PWR_1_o_equal_1_o<19>4_rstpot 
    SLICE_X2Y29.CLK      Tas                   0.349   key_scan<2> 
                                                       key_scan_2_dpot1 
                                                       key_scan_2 
    -------------------------------------------------  --------------------------- 
    Total                                      3.802ns (1.268ns logic, 2.534ns route) 
                                                       (33.4% logic, 66.6% route) 
 
-------------------------------------------------------------------------------- 
 
Paths for end point key_scan_3 (SLICE_X2Y30.D4), 14 paths 
-------------------------------------------------------------------------------- 
Slack (setup path):     16.202ns (requirement - (data path - clock path skew + uncertainty)) 
  Source:               count_2 (FF) 
  Destination:          key_scan_3 (FF) 
  Requirement:          20.000ns 
  Data Path Delay:      3.755ns (Levels of Logic = 3) 
  Clock Path Skew:      -0.008ns (0.340 - 0.348) 
  Source Clock:         clk_BUFGP rising at 0.000ns 
  Destination Clock:    clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.035ns 
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
    Total System Jitter (TSJ):  0.070ns 
    Total Input Jitter (TIJ):   0.000ns 
    Discrete Jitter (DJ):       0.000ns 
    Phase Error (PE):           0.000ns 
 
  Maximum Data Path at Slow Process Corner: count_2 to key_scan_3 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X7Y29.DQ       Tcko                  0.430   count<2> 
                                                       count_2 
    SLICE_X4Y29.D5       net (fanout=3)        1.043   count<2> 
    SLICE_X4Y29.D        Tilo                  0.254   count<19> 
                                                       count[19]_PWR_1_o_equal_1_o<19>2_1 
    SLICE_X2Y29.B1       net (fanout=1)        0.959   count[19]_PWR_1_o_equal_1_o<19>21 
    SLICE_X2Y29.B        Tilo                  0.235   key_scan<2> 
                                                       count[19]_PWR_1_o_equal_1_o<19>4_rstpot 
    SLICE_X2Y30.D4       net (fanout=4)        0.485   count[19]_PWR_1_o_equal_1_o<19>4_rstpot 
    SLICE_X2Y30.CLK      Tas                   0.349   key_scan<3> 
                                                       key_scan_3_dpot1 
                                                       key_scan_3 
    -------------------------------------------------  --------------------------- 
    Total                                      3.755ns (1.268ns logic, 2.487ns route) 
                                                       (33.8% logic, 66.2% route) 
 
-------------------------------------------------------------------------------- 
Slack (setup path):     16.207ns (requirement - (data path - clock path skew + uncertainty)) 
  Source:               count_3 (FF) 
  Destination:          key_scan_3 (FF) 
  Requirement:          20.000ns 
  Data Path Delay:      3.754ns (Levels of Logic = 3) 
  Clock Path Skew:      -0.004ns (0.340 - 0.344) 
  Source Clock:         clk_BUFGP rising at 0.000ns 
  Destination Clock:    clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.035ns 
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
    Total System Jitter (TSJ):  0.070ns 
    Total Input Jitter (TIJ):   0.000ns 
    Discrete Jitter (DJ):       0.000ns 
    Phase Error (PE):           0.000ns 
 
  Maximum Data Path at Slow Process Corner: count_3 to key_scan_3 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X7Y27.AQ       Tcko                  0.430   count<6> 
                                                       count_3 
    SLICE_X4Y29.D2       net (fanout=3)        1.042   count<3> 
    SLICE_X4Y29.D        Tilo                  0.254   count<19> 
                                                       count[19]_PWR_1_o_equal_1_o<19>2_1 
    SLICE_X2Y29.B1       net (fanout=1)        0.959   count[19]_PWR_1_o_equal_1_o<19>21 
    SLICE_X2Y29.B        Tilo                  0.235   key_scan<2> 
                                                       count[19]_PWR_1_o_equal_1_o<19>4_rstpot 
    SLICE_X2Y30.D4       net (fanout=4)        0.485   count[19]_PWR_1_o_equal_1_o<19>4_rstpot 
    SLICE_X2Y30.CLK      Tas                   0.349   key_scan<3> 
                                                       key_scan_3_dpot1 
                                                       key_scan_3 
    -------------------------------------------------  --------------------------- 
    Total                                      3.754ns (1.268ns logic, 2.486ns route) 
                                                       (33.8% logic, 66.2% route) 
 
-------------------------------------------------------------------------------- 
Slack (setup path):     16.237ns (requirement - (data path - clock path skew + uncertainty)) 
  Source:               count_0 (FF) 
  Destination:          key_scan_3 (FF) 
  Requirement:          20.000ns 
  Data Path Delay:      3.720ns (Levels of Logic = 3) 
  Clock Path Skew:      -0.008ns (0.340 - 0.348) 
  Source Clock:         clk_BUFGP rising at 0.000ns 
  Destination Clock:    clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.035ns 
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
    Total System Jitter (TSJ):  0.070ns 
    Total Input Jitter (TIJ):   0.000ns 
    Discrete Jitter (DJ):       0.000ns 
    Phase Error (PE):           0.000ns 
 
  Maximum Data Path at Slow Process Corner: count_0 to key_scan_3 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X7Y29.AQ       Tcko                  0.430   count<2> 
                                                       count_0 
    SLICE_X4Y29.D1       net (fanout=3)        1.008   count<0> 
    SLICE_X4Y29.D        Tilo                  0.254   count<19> 
                                                       count[19]_PWR_1_o_equal_1_o<19>2_1 
    SLICE_X2Y29.B1       net (fanout=1)        0.959   count[19]_PWR_1_o_equal_1_o<19>21 
    SLICE_X2Y29.B        Tilo                  0.235   key_scan<2> 
                                                       count[19]_PWR_1_o_equal_1_o<19>4_rstpot 
    SLICE_X2Y30.D4       net (fanout=4)        0.485   count[19]_PWR_1_o_equal_1_o<19>4_rstpot 
    SLICE_X2Y30.CLK      Tas                   0.349   key_scan<3> 
                                                       key_scan_3_dpot1 
                                                       key_scan_3 
    -------------------------------------------------  --------------------------- 
    Total                                      3.720ns (1.268ns logic, 2.452ns route) 
                                                       (34.1% logic, 65.9% route) 
 
-------------------------------------------------------------------------------- 
 
Paths for end point key_scan_1 (SLICE_X2Y29.C4), 14 paths 
-------------------------------------------------------------------------------- 
Slack (setup path):     16.296ns (requirement - (data path - clock path skew + uncertainty)) 
  Source:               count_2 (FF) 
  Destination:          key_scan_1 (FF) 
  Requirement:          20.000ns 
  Data Path Delay:      3.660ns (Levels of Logic = 3) 
  Clock Path Skew:      -0.009ns (0.339 - 0.348) 
  Source Clock:         clk_BUFGP rising at 0.000ns 
  Destination Clock:    clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.035ns 
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
    Total System Jitter (TSJ):  0.070ns 
    Total Input Jitter (TIJ):   0.000ns 
    Discrete Jitter (DJ):       0.000ns 
    Phase Error (PE):           0.000ns 
 
  Maximum Data Path at Slow Process Corner: count_2 to key_scan_1 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X7Y29.DQ       Tcko                  0.430   count<2> 
                                                       count_2 
    SLICE_X4Y29.D5       net (fanout=3)        1.043   count<2> 
    SLICE_X4Y29.D        Tilo                  0.254   count<19> 
                                                       count[19]_PWR_1_o_equal_1_o<19>2_1 
    SLICE_X2Y29.B1       net (fanout=1)        0.959   count[19]_PWR_1_o_equal_1_o<19>21 
    SLICE_X2Y29.B        Tilo                  0.235   key_scan<2> 
                                                       count[19]_PWR_1_o_equal_1_o<19>4_rstpot 
    SLICE_X2Y29.C4       net (fanout=4)        0.390   count[19]_PWR_1_o_equal_1_o<19>4_rstpot 
    SLICE_X2Y29.CLK      Tas                   0.349   key_scan<2> 
                                                       key_scan_1_dpot1 
                                                       key_scan_1 
    -------------------------------------------------  --------------------------- 
    Total                                      3.660ns (1.268ns logic, 2.392ns route) 
                                                       (34.6% logic, 65.4% route) 
 
-------------------------------------------------------------------------------- 
Slack (setup path):     16.301ns (requirement - (data path - clock path skew + uncertainty)) 
  Source:               count_3 (FF) 
  Destination:          key_scan_1 (FF) 
  Requirement:          20.000ns 
  Data Path Delay:      3.659ns (Levels of Logic = 3) 
  Clock Path Skew:      -0.005ns (0.339 - 0.344) 
  Source Clock:         clk_BUFGP rising at 0.000ns 
  Destination Clock:    clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.035ns 
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
    Total System Jitter (TSJ):  0.070ns 
    Total Input Jitter (TIJ):   0.000ns 
    Discrete Jitter (DJ):       0.000ns 
    Phase Error (PE):           0.000ns 
 
  Maximum Data Path at Slow Process Corner: count_3 to key_scan_1 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X7Y27.AQ       Tcko                  0.430   count<6> 
                                                       count_3 
    SLICE_X4Y29.D2       net (fanout=3)        1.042   count<3> 
    SLICE_X4Y29.D        Tilo                  0.254   count<19> 
                                                       count[19]_PWR_1_o_equal_1_o<19>2_1 
    SLICE_X2Y29.B1       net (fanout=1)        0.959   count[19]_PWR_1_o_equal_1_o<19>21 
    SLICE_X2Y29.B        Tilo                  0.235   key_scan<2> 
                                                       count[19]_PWR_1_o_equal_1_o<19>4_rstpot 
    SLICE_X2Y29.C4       net (fanout=4)        0.390   count[19]_PWR_1_o_equal_1_o<19>4_rstpot 
    SLICE_X2Y29.CLK      Tas                   0.349   key_scan<2> 
                                                       key_scan_1_dpot1 
                                                       key_scan_1 
    -------------------------------------------------  --------------------------- 
    Total                                      3.659ns (1.268ns logic, 2.391ns route) 
                                                       (34.7% logic, 65.3% route) 
 
-------------------------------------------------------------------------------- 
Slack (setup path):     16.331ns (requirement - (data path - clock path skew + uncertainty)) 
  Source:               count_0 (FF) 
  Destination:          key_scan_1 (FF) 
  Requirement:          20.000ns 
  Data Path Delay:      3.625ns (Levels of Logic = 3) 
  Clock Path Skew:      -0.009ns (0.339 - 0.348) 
  Source Clock:         clk_BUFGP rising at 0.000ns 
  Destination Clock:    clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.035ns 
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
    Total System Jitter (TSJ):  0.070ns 
    Total Input Jitter (TIJ):   0.000ns 
    Discrete Jitter (DJ):       0.000ns 
    Phase Error (PE):           0.000ns 
 
  Maximum Data Path at Slow Process Corner: count_0 to key_scan_1 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X7Y29.AQ       Tcko                  0.430   count<2> 
                                                       count_0 
    SLICE_X4Y29.D1       net (fanout=3)        1.008   count<0> 
    SLICE_X4Y29.D        Tilo                  0.254   count<19> 
                                                       count[19]_PWR_1_o_equal_1_o<19>2_1 
    SLICE_X2Y29.B1       net (fanout=1)        0.959   count[19]_PWR_1_o_equal_1_o<19>21 
    SLICE_X2Y29.B        Tilo                  0.235   key_scan<2> 
                                                       count[19]_PWR_1_o_equal_1_o<19>4_rstpot 
    SLICE_X2Y29.C4       net (fanout=4)        0.390   count[19]_PWR_1_o_equal_1_o<19>4_rstpot 
    SLICE_X2Y29.CLK      Tas                   0.349   key_scan<2> 
                                                       key_scan_1_dpot1 
                                                       key_scan_1 
    -------------------------------------------------  --------------------------- 
    Total                                      3.625ns (1.268ns logic, 2.357ns route) 
                                                       (35.0% logic, 65.0% route) 
 
-------------------------------------------------------------------------------- 
 
Hold Paths: TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_pin" 50 MHz HIGH 50%; 
-------------------------------------------------------------------------------- 
 
Paths for end point key_scan_0 (SLICE_X2Y29.A6), 1 path 
-------------------------------------------------------------------------------- 
Slack (hold path):      0.414ns (requirement - (clock path skew + uncertainty - data path)) 
  Source:               key_scan_0 (FF) 
  Destination:          key_scan_0 (FF) 
  Requirement:          0.000ns 
  Data Path Delay:      0.414ns (Levels of Logic = 1) 
  Clock Path Skew:      0.000ns 
  Source Clock:         clk_BUFGP rising at 20.000ns 
  Destination Clock:    clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.000ns 
 
  Minimum Data Path at Fast Process Corner: key_scan_0 to key_scan_0 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X2Y29.AQ       Tcko                  0.200   key_scan<2> 
                                                       key_scan_0 
    SLICE_X2Y29.A6       net (fanout=3)        0.024   key_scan<0> 
    SLICE_X2Y29.CLK      Tah         (-Th)    -0.190   key_scan<2> 
                                                       key_scan_0_dpot1 
                                                       key_scan_0 
    -------------------------------------------------  --------------------------- 
    Total                                      0.414ns (0.390ns logic, 0.024ns route) 
                                                       (94.2% logic, 5.8% route) 
 
-------------------------------------------------------------------------------- 
 
Paths for end point key_scan_2 (SLICE_X2Y29.D6), 1 path 
-------------------------------------------------------------------------------- 
Slack (hold path):      0.416ns (requirement - (clock path skew + uncertainty - data path)) 
  Source:               key_scan_2 (FF) 
  Destination:          key_scan_2 (FF) 
  Requirement:          0.000ns 
  Data Path Delay:      0.416ns (Levels of Logic = 1) 
  Clock Path Skew:      0.000ns 
  Source Clock:         clk_BUFGP rising at 20.000ns 
  Destination Clock:    clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.000ns 
 
  Minimum Data Path at Fast Process Corner: key_scan_2 to key_scan_2 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X2Y29.DQ       Tcko                  0.200   key_scan<2> 
                                                       key_scan_2 
    SLICE_X2Y29.D6       net (fanout=3)        0.026   key_scan<2> 
    SLICE_X2Y29.CLK      Tah         (-Th)    -0.190   key_scan<2> 
                                                       key_scan_2_dpot1 
                                                       key_scan_2 
    -------------------------------------------------  --------------------------- 
    Total                                      0.416ns (0.390ns logic, 0.026ns route) 
                                                       (93.8% logic, 6.3% route) 
 
-------------------------------------------------------------------------------- 
 
Paths for end point key_scan_3 (SLICE_X2Y30.D6), 1 path 
-------------------------------------------------------------------------------- 
Slack (hold path):      0.416ns (requirement - (clock path skew + uncertainty - data path)) 
  Source:               key_scan_3 (FF) 
  Destination:          key_scan_3 (FF) 
  Requirement:          0.000ns 
  Data Path Delay:      0.416ns (Levels of Logic = 1) 
  Clock Path Skew:      0.000ns 
  Source Clock:         clk_BUFGP rising at 20.000ns 
  Destination Clock:    clk_BUFGP rising at 20.000ns 
  Clock Uncertainty:    0.000ns 
 
  Minimum Data Path at Fast Process Corner: key_scan_3 to key_scan_3 
    Location             Delay type         Delay(ns)  Physical Resource 
                                                       Logical Resource(s) 
    -------------------------------------------------  ------------------- 
    SLICE_X2Y30.DQ       Tcko                  0.200   key_scan<3> 
                                                       key_scan_3 
    SLICE_X2Y30.D6       net (fanout=3)        0.026   key_scan<3> 
    SLICE_X2Y30.CLK      Tah         (-Th)    -0.190   key_scan<3> 
                                                       key_scan_3_dpot1 
                                                       key_scan_3 
    -------------------------------------------------  --------------------------- 
    Total                                      0.416ns (0.390ns logic, 0.026ns route) 
                                                       (93.8% logic, 6.3% route) 
 
-------------------------------------------------------------------------------- 
 
Component Switching Limit Checks: TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_pin" 50 MHz HIGH 50%; 
-------------------------------------------------------------------------------- 
Slack: 17.334ns (period - min period limit) 
  Period: 20.000ns 
  Min period limit: 2.666ns (375.094MHz) (Tbcper_I) 
  Physical resource: clk_BUFGP/BUFG/I0 
  Logical resource: clk_BUFGP/BUFG/I0 
  Location pin: BUFGMUX_X3Y13.I0 
  Clock network: clk_BUFGP/IBUFG 
-------------------------------------------------------------------------------- 
Slack: 19.520ns (period - min period limit) 
  Period: 20.000ns 
  Min period limit: 0.480ns (2083.333MHz) (Tcp) 
  Physical resource: count<19>/CLK 
  Logical resource: count_19/CK 
  Location pin: SLICE_X4Y29.CLK 
  Clock network: clk_BUFGP 
-------------------------------------------------------------------------------- 
Slack: 19.520ns (period - (min high pulse limit / (high pulse / period))) 
  Period: 20.000ns 
  High pulse: 10.000ns 
  High pulse limit: 0.240ns (Trpw) 
  Physical resource: count<19>/SR 
  Logical resource: count_19/SR 
  Location pin: SLICE_X4Y29.SR 
  Clock network: rst_n_inv 
-------------------------------------------------------------------------------- 
 
 
All constraints were met. 
 
 
Data Sheet report: 
----------------- 
All values displayed in nanoseconds (ns) 
 
Clock to Setup on destination clock clk 
---------------+---------+---------+---------+---------+ 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall| 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| 
---------------+---------+---------+---------+---------+ 
clk            |    3.881|         |         |         | 
---------------+---------+---------+---------+---------+ 
 
 
Timing summary: 
--------------- 
 
Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0) 
 
Constraints cover 710 paths, 0 nets, and 215 connections 
 
Design statistics: 
   Minimum period:   3.881ns{1}   (Maximum frequency: 257.666MHz) 
 
 
------------------------------------Footnotes----------------------------------- 
1)  The minimum period statistic assumes all single cycle delays. 
 
Analysis completed Fri Sep 25 14:39:46 2015  
-------------------------------------------------------------------------------- 
 
Trace Settings: 
------------------------- 
Trace Settings  
 
Peak Memory Usage: 213 MB