www.pudn.com > 05_key_test.rar > trce.xmsgs, change:2015-09-29,size:1030b

<?xml version="1.0" encoding="UTF-8"?> 
<!-- IMPORTANT: This is an internal file that has been generated 
     by the Xilinx ISE software.  Any direct editing or 
     changes made to this file may result in unpredictable 
     behavior or data corruption.  It is strongly advised that 
     users do not edit the contents of this file. --> 
<msg type="info" file="Timing" num="3412" delta="old" >To improve timing, see the Timing Closure User Guide (UG612).</msg> 

<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg> 

<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>