www.pudn.com > v_ycrcb2rgb_v6_01_a.rar > ycrcb2rgb_top.vhd, change:2012-12-05,size:17764b


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---------------------------------------------------------------
-- Synthesizable model
---------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all; --for integer to std_logic_vector conversions
use ieee.std_logic_unsigned.all; --for integer to std_logic_vector conversions

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--use UNISIM.VPKG.ALL;

library v_tc_v5_01_a;

library v_ycrcb2rgb_v6_01_a;
use v_ycrcb2rgb_v6_01_a.genxlib_utils.all;
use v_ycrcb2rgb_v6_01_a.ycrcb2rgb_axi4s_control_pkg.all;
USE v_ycrcb2rgb_v6_01_a.ycrcb2rgb_pkg.all;

entity ycrcb2rgb_top is
  generic(
     C_HAS_AXI4_LITE            : integer range 0 to 1 := 0;   -- Interface 1=AXI4-Lite, 0=Constant
     C_HAS_DEBUG                : integer range 0 to 1 := 0;   -- Adds Debug features 
     C_S_AXIS_VIDEO_DATA_WIDTH  : integer := 8;     -- Input Width: (8, 10, 12)
     C_S_AXIS_VIDEO_FORMAT	: integer := 2;     -- Input Video Format: 1=YUV444, 2=RGB
     C_S_AXIS_VIDEO_TDATA_WIDTH	: integer := 24;    -- Output VoAXI4-St Data Width
     C_M_AXIS_VIDEO_DATA_WIDTH  : integer := 8;     -- Output Width: (8, 10, 12)
     C_M_AXIS_VIDEO_FORMAT	: integer := 2;     -- Output Video Format: 1=YUV444, 2=RGB
     C_M_AXIS_VIDEO_TDATA_WIDTH	: integer := 24;    -- Output VoAXI4-St Data Width
     C_ACTIVE_COLS              : integer := 1920;  -- Default is 1080p
     C_ACTIVE_ROWS              : integer := 1080;  --
     C_MWIDTH                   : integer := 23;    --
     C_COEF_RANGE               : integer := 1;     --
     C_ACOEF                    : integer := 91907; -- Coefficient derived from CA
     C_BCOEF                    : integer := -46751; -- Coefficient derived from CB
     C_CCOEF                    : integer := -22503; -- Coefficient derived from CC
     C_DCOEF                    : integer := 116156; -- Coefficient derived from CD
     C_ROFFSET                  : integer := -45953; -- R Offset compensation
     C_GOFFSET                  : integer := 34627;  -- G Offset compensation
     C_BOFFSET                  : integer := -58077; -- B Offset compensation
     C_HAS_CLIP                 : integer range 0 to 1 := 1;    -- 0=No Clip, 1=Clip
     C_HAS_CLAMP                : integer range 0 to 1 := 1;    -- 0=No Clamp, 1=Clamp
     C_RGBMAX                   : integer := 255;    -- Y Clipping value
     C_RGBMIN                   : integer := 0;      -- Y Clamping value
     --From Coregen
     C_FAMILY : string := "virtex6"
  );
  port (
     clk                 : in  std_logic;
     ce                  : in  std_logic;
     sclr                : in  std_logic;
     core_d              : in  std_logic := '0';
     s_axis_tdata        : in  std_logic_vector(C_S_AXIS_VIDEO_TDATA_WIDTH-1 downto 0 ) := (OTHERS => '0');
     s_axis_tvalid       : in  std_logic:= '0';
     s_axis_tlast        : in  std_logic:= '0';
     s_axis_tuser_sof    : in  std_logic:= '0';
     s_axis_tready       : out std_logic;
     m_axis_tdata        : out std_logic_vector(C_M_AXIS_VIDEO_TDATA_WIDTH-1 downto 0 ) := (OTHERS => '0');
     m_axis_tvalid       : out std_logic:= '0';
     m_axis_tlast        : out std_logic:= '0';
     m_axis_tuser_sof    : out std_logic:= '0';
     m_axis_tready       : in  std_logic:= '1'; 

     register_update     : out std_logic:= '0';
     control             : in  std_logic_vector(31 downto 0) := conv_std_logic_vector(1, 32);  -- SW Enabled
     status              : out std_logic_vector(16 downto 0) := (others => '0');
     error               : out std_logic_vector( 3 downto 0) := (others => '0');
     sysdebug_0          : out std_logic_vector(31 downto 0) := (others => '0');
     sysdebug_1          : out std_logic_vector(31 downto 0) := (others => '0');
     sysdebug_2          : out std_logic_vector(31 downto 0) := (others => '0');    
     active_rows         : in  std_logic_vector(12 downto 0) := conv_std_logic_vector(C_ACTIVE_ROWS, 13);
     active_cols         : in  std_logic_vector(12 downto 0) := conv_std_logic_vector(C_ACTIVE_COLS, 13);
     rgbmax              : in  std_logic_vector(15 downto 0) := conv_std_logic_vector(C_RGBMAX,  16);  --100
     rgbmin              : in  std_logic_vector(15 downto 0) := conv_std_logic_vector(C_RGBMIN,  16);  --104
     roffset             : in  std_logic_vector(31 downto 0) := conv_std_logic_vector(C_ROFFSET, 32);  --118
     goffset             : in  std_logic_vector(31 downto 0) := conv_std_logic_vector(C_GOFFSET, 32);  --11c
     boffset             : in  std_logic_vector(31 downto 0) := conv_std_logic_vector(C_BOFFSET, 32);  --120
     acoef               : in  std_logic_vector(16 downto 0) := conv_std_logic_vector(C_ACOEF,   17);  --124
     bcoef               : in  std_logic_vector(16 downto 0) := conv_std_logic_vector(C_BCOEF,   17);  --128
     ccoef               : in  std_logic_vector(16 downto 0) := conv_std_logic_vector(C_CCOEF,   17);  --12C
     dcoef               : in  std_logic_vector(16 downto 0) := conv_std_logic_vector(C_DCOEF,   17)   --130
  );
end ycrcb2rgb_top;



architecture synth of ycrcb2rgb_top is

  constant LINE_FLUSH_CLKS1   : integer := YCrCb2RGB_LATENCY(1,1,C_HAS_CLIP, C_HAS_CLAMP);  -- Enter the number of CLK cycles the core needs to flush out pipelines (or generate extra pixels per line)   TYPICALLY THIS IS YOUR CORE PIPELINE DELAY
  constant DATA_VALID_CLKS1   : integer := YCrCb2RGB_LATENCY(1,1,C_HAS_CLIP, C_HAS_CLAMP);  -- Enter the number of CLK cycles the core needs until valid data starts to emerge                            TYPICALLY THIS IS YOUR CORE PIPELINE DELAY 

  alias S_WIDTH                : integer is C_S_AXIS_VIDEO_DATA_WIDTH;
  alias M_WIDTH                : integer is C_M_AXIS_VIDEO_DATA_WIDTH;
  constant S_BUS_WIDTH         : integer := C_S_AXIS_VIDEO_DATA_WIDTH*3;
  constant M_BUS_WIDTH         : integer := C_M_AXIS_VIDEO_DATA_WIDTH*3;

  -----------------------------------------------------------------------------
  -- Internal CCM Core
  -----------------------------------------------------------------------------

  signal core_ce                : std_logic := '1';
  signal axi_resetn             : std_logic := '1';
  signal video_data_out_i       : std_logic_vector (M_BUS_WIDTH-1 downto 0 ) := (OTHERS => '0');
  signal video_data_in_i        : std_logic_vector (S_BUS_WIDTH-1 downto 0 ) := (OTHERS => '0');
  signal vid_data_in_reform     : std_logic_vector (M_BUS_WIDTH-1 downto 0 ) := (OTHERS => '0');
  signal intcore_data_out       : std_logic_vector (M_BUS_WIDTH-1 downto 0 ) := (OTHERS => '0');
                                
  signal master_en              : std_logic := '1';
                                                               
  signal vid_data_in            : std_logic_vector(S_BUS_WIDTH-1 downto 0) := (OTHERS => '0');
  signal vid_eol_in             : std_logic := '0';
  signal vid_sof_in             : std_logic := '0';
  signal vid_data_in_r          : std_logic_vector(S_BUS_WIDTH-1 downto 0) := (OTHERS => '0');
  signal vid_eol_in_r           : std_logic := '0';
  signal vid_sof_in_r           : std_logic := '0';
  signal vid_empty_in           : std_logic := '0';
  signal vid_re_in              : std_logic := '0';

  signal debug_data_out         : std_logic_vector(M_BUS_WIDTH-1 downto 0) := (OTHERS => '0');
  signal debug_eol_out          : std_logic := '0';
  signal debug_sof_out          : std_logic := '0';
  signal debug_valid_out        : std_logic := '0';
  signal debug_we_out_masked    : std_logic := '0';
                                
  signal vid_we_out             : std_logic := '0';
  signal vid_eol_out            : std_logic := '0';
  signal vid_sof_out            : std_logic := '0';  
  signal vid_eof_out            : std_logic := '0';
  signal vid_afull_out          : std_logic := '0';
  
  signal sof                    : std_logic := '0';   -- Start of frame
  signal eof                    : std_logic := '0';   -- End of frame

  signal ycrcb2rgb_update_i         : std_logic := '0';

  alias  SW_ENABLE              : std_logic is control(0);
  alias  REG_UPDATE             : std_logic is control(1);
  alias  BYPASS                 : std_logic is control(4);
  alias  TEST_PATTERN           : std_logic is control(5);
  alias  SOF_SYNCED_RESET       : std_logic is control(30);
  alias  SW_RESET               : std_logic is control(31);
                                               
  alias  PROC_STARTED           : std_logic is status(0);
  alias  FRAME_COMPLETE         : std_logic is status(1);
  alias  PIXEL_CNT_TC           : std_logic is status(2);
  alias  LINE_CNT_TC            : std_logic is status(3);
  alias  SLAVE_0_ERROR          : std_logic is status(16);
                                               
  alias  SLAVE_0_EOL_EARLY      : std_logic is error(0);
  alias  SLAVE_0_EOL_LATE       : std_logic is error(1);
  alias  SLAVE_0_SOF_EARLY      : std_logic is error(2);
  alias  SLAVE_0_SOF_LATE       : std_logic is error(3);
    
begin

  axi_in_fifo: entity v_ycrcb2rgb_v6_01_a.axis_input_buffer
  generic map(
    C_AXIS_BUFFER_DEPTH   => 16,
    C_AXIS_DATA_WIDTH     => S_BUS_WIDTH)
  port map(
    clk                   => clk,
    ce                    => master_en,
    sclr                  => sclr,
    s_axis_tdata          => s_axis_tdata(S_BUS_WIDTH-1 downto 0),
    s_axis_tvalid         => s_axis_tvalid,
    s_axis_tlast          => s_axis_tlast,
    s_axis_tuser_sof      => s_axis_tuser_sof,
    s_axis_tready         => s_axis_tready,
    vid_data_out          => vid_data_in,
    vid_eol_out           => vid_eol_in,
    vid_sof_out           => vid_sof_in,
    vid_empty_out         => vid_empty_in,
    vid_re_in             => vid_re_in );

  -- Generate master enable for the core:
  master_en <= SW_ENABLE and ce;

  delay_proc : process(clk)
  begin
    if rising_edge(clk) then
      if core_ce = '1' then
        vid_data_in_r <= vid_data_in;
        vid_eol_in_r  <= vid_eol_in;
        vid_sof_in_r  <= vid_sof_in;
      end if; --core_ce
    end if; --clk
  end process;    

  axi_control: entity v_tc_v5_01_a.axi4s_control
    generic map ( 
      C_DEBUG             => C_HAS_DEBUG,
      LINE_FLUSH_CLKS     => LINE_FLUSH_CLKS1,
      DATA_VALID_CLKS     => DATA_VALID_CLKS1,
      FRAME_FLUSH_LINES   => FRAME_FLUSH_LINES,
      DATA_VALID_LINES    => DATA_VALID_LINES
    )
    port map(
      clk                 => clk,
      ce                  => master_en,
      sclr                => sclr,
      bypass              => BYPASS, 
      test_pattern        => TEST_PATTERN,
      in_fifo_eol         => vid_eol_in,  
      in_fifo_sof         => vid_sof_in,
      in_fifo_empty       => vid_empty_in,
      in_fifo_re          => vid_re_in,
      out_fifo_eol        => vid_eol_out,   
      out_fifo_sof        => vid_sof_out,   
      out_fifo_afull      => vid_afull_out, 
      out_fifo_we         => vid_we_out,
      core_ce             => core_ce,
      eof                 => vid_eof_out,
      pixel_cnt_tc        => PIXEL_CNT_TC,
      line_cnt_tc         => LINE_CNT_TC,
      sof_early           => SLAVE_0_SOF_EARLY,
      sof_late            => SLAVE_0_SOF_LATE,
      eol_early           => SLAVE_0_EOL_EARLY,
      eol_late            => SLAVE_0_EOL_LATE,
      slave_error         => SLAVE_0_ERROR,
      active_rows         => active_rows,
      active_cols         => active_cols );


--Instantiate the core functionality
  intcore : entity v_ycrcb2rgb_v6_01_a.ycrcb2rgb_core
    generic map (
      C_IWIDTH         => C_S_AXIS_VIDEO_DATA_WIDTH,
      C_OWIDTH         => C_M_AXIS_VIDEO_DATA_WIDTH,
      C_MWIDTH         => C_MWIDTH,
      C_COEF_RANGE     => C_COEF_RANGE,
      C_HAS_CLIP       => C_HAS_CLIP, 
      C_HAS_CLAMP      => C_HAS_CLAMP
    )
    port map (
      clk            => clk,
      ce             => core_ce,
      sclr           => sclr,
      video_data_in  => vid_data_in_r,
      video_data_out => intcore_data_out,
      rgbmax         => rgbmax,
      rgbmin         => rgbmin,
      roffset        => roffset,
      goffset        => goffset,
      boffset        => boffset,
      acoef          => acoef,
      bcoef          => bcoef,
      ccoef          => ccoef,
      dcoef          => dcoef
    );

  has_debug: if (C_HAS_AXI4_LITE/=0) and (C_HAS_DEBUG>0) generate

    -- Generate register update for the core:
    register_update <= (vid_sof_in and REG_UPDATE) or TEST_PATTERN;

    -- Repackage 3 channel IWIDTH wide data to 3*OWIDTH bits:
    VID_DATA_PROC : process(vid_data_in) is
    begin
      for i in 1 to 3 loop
        vid_data_in_reform(i*M_WIDTH-1 downto (i-1)*M_WIDTH+max(0,M_WIDTH-S_WIDTH)) <= vid_data_in(i*S_WIDTH-1 downto (i-1)*S_WIDTH+max(0,S_WIDTH-M_WIDTH));
      end loop;
    end process VID_DATA_PROC;

    debug_module: entity v_ycrcb2rgb_v6_01_a.debug 
      generic map(
        DATA_WIDTH                 => C_M_AXIS_VIDEO_DATA_WIDTH,
        C_M_AXIS_VIDEO_TDATA_WIDTH => C_M_AXIS_VIDEO_TDATA_WIDTH,
        C_M_AXIS_VIDEO_FORMAT      => C_M_AXIS_VIDEO_FORMAT)
      port map(
        clk                   => clk,
        ce                    => master_en,
        sclr                  => sclr,                             
        test_pattern          => TEST_PATTERN,
        bypass                => BYPASS,                              
        active_rows           => active_rows,
        active_cols           => active_cols,
        out_fifo_afull        => vid_afull_out,
        vid_data_in           => vid_data_in_reform,
        vid_valid_in          => core_ce,
        vid_eol_in            => vid_eol_in,
        vid_sof_in            => vid_sof_in,
        core_data_in          => intcore_data_out,
        core_valid_in         => vid_we_out,
        core_eol_in           => vid_eol_out,
        core_sof_in           => vid_sof_out,
        core_eof_in           => vid_eof_out,
        sysdebug0             => sysdebug_0,
        sysdebug1             => sysdebug_1,
        sysdebug2             => sysdebug_2,
        vid_data_out          => debug_data_out,
        vid_valid_out         => debug_valid_out,
        vid_eol_out           => debug_eol_out,
        vid_sof_out           => debug_sof_out);
  end generate;

  no_debug: if (C_HAS_AXI4_LITE=0) or (C_HAS_DEBUG<=0) generate
    -- Generate register update for the core:
    register_update <= vid_sof_in and REG_UPDATE;

    debug_data_out  <= intcore_data_out;  
    debug_valid_out <= vid_we_out;
    debug_eol_out   <= vid_eol_out;
    debug_sof_out   <= vid_sof_out;
  end generate;

  debug_we_out_masked <= debug_valid_out and not core_d;
  
  axi_out_fifo: entity v_ycrcb2rgb_v6_01_a.axis_output_buffer
    generic map(
      C_AXIS_BUFFER_DEPTH => 16,
      C_AXIS_DATA_WIDTH   => M_BUS_WIDTH)
    port map(
      clk                 => clk,
      sclr                => sclr,
      ce                  => master_en,
      vid_data_in         => debug_data_out,
      vid_valid_in        => debug_we_out_masked,
      vid_eol_in          => debug_eol_out,
      vid_sof_in          => debug_sof_out,
      vid_afull_out       => vid_afull_out,
      m_axis_tready       => m_axis_tready,
      m_axis_tvalid       => m_axis_tvalid,
      m_axis_tlast        => m_axis_tlast,
      m_axis_tuser_sof    => m_axis_tuser_sof,
      m_axis_tdata        => m_axis_tdata(M_BUS_WIDTH-1 downto 0)  );

  -- Assign remaining status outputs:
  PROC_STARTED    <= core_ce;
  FRAME_COMPLETE  <= vid_eof_out;


end synth;