www.pudn.com > v_ycrcb2rgb_v6_01_a.rar > v_ycrcb2rgb.vhd, change:2012-12-05,size:22569b


-- $Id: v_ycrcb2rgb.vhd,v 1.1 2011/04/11 10:39:05 Exp $
--
-- (c) Copyright 2011 Xilinx, Inc. All rights reserved.
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--  All rights reserved.


library IEEE;
use IEEE.std_logic_1164.ALL;
use ieee.std_logic_arith.all; --for integer to std_logic_vector conversions
use ieee.std_logic_unsigned.all; --for integer to std_logic_vector conversions


library v_ycrcb2rgb_v6_01_a;

library v_tc_v5_01_a;
use v_tc_v5_01_a.video_ctrl_pkg.all;


entity v_ycrcb2rgb is
  generic(
    -- Generic parameters (required by all interfaces):
    C_S_AXIS_VIDEO_DATA_WIDTH	: integer := 8  ;   -- Input Width: (8, 10, 12)
    C_S_AXIS_VIDEO_FORMAT	: integer := 1  ;   -- Input Video Format: 1=YUV444, 2=RGB
    C_S_AXIS_VIDEO_TDATA_WIDTH	: integer := 24 ;   -- Input VoAXI4-St Data Width
    C_M_AXIS_VIDEO_DATA_WIDTH	: integer := 8  ;   -- Output Width: (8, 10, 12)
    C_M_AXIS_VIDEO_FORMAT	: integer := 2  ;   -- Output Video Format: 1=YUV444, 2=RGB
    C_M_AXIS_VIDEO_TDATA_WIDTH	: integer := 24 ;   -- Output VoAXI4-St Data Width
    C_HAS_AXI4_LITE             : integer range 0 to 1 := 0;     -- Interface 1=AXI4-Lite, 0=Constant
    C_HAS_DEBUG                 : integer range 0 to 1 := 0;     -- Controls instantiation of Debug circuit
    C_HAS_INTC_IF               : integer range 0 to 1 := 0;     -- Controls instantiation of INTC IF
    C_MAX_COLS                  : integer := 1920;  -- Max number of pixels
    C_ACTIVE_COLS               : integer := 1920;  -- Default is 1080p
    C_ACTIVE_ROWS               : integer := 1080;  --

    C_MWIDTH                    : integer := 25;     --
    C_COEF_RANGE                : integer := 2;      --
    C_ACOEF                     : integer :=  22978; -- Coefficient derived from CA
    C_BCOEF                     : integer := -11704; -- Coefficient derived from CB
    C_CCOEF                     : integer :=  -5641; -- Coefficient derived from CC
    C_DCOEF                     : integer :=  29049; -- Coefficient derived from CD
    C_ROFFSET                   : integer := -6390272; -- Y Offset compensation
    C_GOFFSET                   : integer :=  3932416; -- Cb Offset compensation
    C_BOFFSET                   : integer := -7944448; -- Cr Offset compensation
    C_HAS_CLIP                  : integer := 1;      -- 0=No Clip, 1=Clip
    C_HAS_CLAMP                 : integer := 1;      -- 0=No Clamp, 1=Clamp
    C_RGBMAX                    : integer := 240;    -- Y Clipping value
    C_RGBMIN                    : integer := 16;      -- Y Clamping value
    
    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol parameters, do not add to or delete
--    C_BASEADDR            : std_logic_vector     := X"FFFFFFFF";
--    C_HIGHADDR            : std_logic_vector     := X"00000000";
    C_S_AXI_ADDR_WIDTH    : integer                :=  9; -- AXI4-LITE Addr Width
    C_S_AXI_DATA_WIDTH    : integer range 32 to 64 := 32; -- AXI4-LITE Data Width
    C_S_AXI_CLK_FREQ_HZ   : integer                := 100000000; -- AXI4 Bus Speed
    C_FAMILY              : string                 := "virtex5"  -- FPGA Family
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
    );
  port (
    -- AXI Global System Signals
    aclk                    : in  std_logic; 
    aclken                  : in  std_logic := '1';
    aresetn                 : in  std_logic := '1';
    s_axi_aclk              : in  std_logic := '0'; 
    s_axi_aclken            : in  std_logic := '1';
    s_axi_aresetn           : in  std_logic := '1';
    intc_if                 : out std_logic_vector(8 downto 0):= (OTHERS => '0');
    irq                     : out std_logic:= '0';
    -- Video over AXI4-Stream Slave Input Interface
    s_axis_video_tdata      : in  std_logic_vector(C_S_AXIS_VIDEO_TDATA_WIDTH-1 downto 0 ) := (OTHERS => '0');
    s_axis_video_tready     : out std_logic:= '0';
    s_axis_video_tvalid     : in  std_logic:= '0';
    s_axis_video_tlast      : in  std_logic:= '0';
    s_axis_video_tuser_sof  : in  std_logic:= '0';
    -- Video over AXI4-Stream Master Output Interface
    m_axis_video_tdata      : out std_logic_vector(C_M_AXIS_VIDEO_TDATA_WIDTH-1 downto 0 ) := (OTHERS => '0');
    m_axis_video_tvalid     : out std_logic:= '0';
    m_axis_video_tready     : in  std_logic:= '1';                   
    m_axis_video_tlast      : out std_logic:= '0';
    m_axis_video_tuser_sof  : out std_logic:= '0';
    -- AXI4-Lite Slave Control interface signals :
    -- This AXI4-Lite interface is assumed to be synchronous to axis_aclk 
    -- AXI Write Address Channel Signals
    s_axi_awaddr  : in  std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0) := (others => '0');
    s_axi_awvalid : in  std_logic := '0';
    s_axi_awready : out std_logic;
    -- AXI Write Channel Signals
    s_axi_wdata   : in  std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0) := (others => '0');
    s_axi_wstrb   : in  std_logic_vector
                               (((C_S_AXI_DATA_WIDTH/8)-1) downto 0) := (others => '0');
    s_axi_wvalid  : in  std_logic := '0';
    s_axi_wready  : out std_logic;
    -- AXI Write Response Channel Signals
    s_axi_bresp   : out std_logic_vector(1 downto 0);
    s_axi_bvalid  : out std_logic;
    s_axi_bready  : in  std_logic := '0';
    -- AXI Read Address Channel Signals
    s_axi_araddr  : in  std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0) := (others => '0');
    s_axi_arvalid : in  std_logic := '0';
    s_axi_arready : out std_logic := '0';
    -- AXI Read Data Channel Signals
    s_axi_rdata   : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
    s_axi_rresp   : out std_logic_vector(1 downto 0);
    s_axi_rvalid  : out std_logic;
    s_axi_rready  : in  std_logic := '0'  --;
  );

  attribute SIGIS : string;
  attribute SIGIS of aclk         : signal is "CLK";
  attribute SIGIS of aresetn      : signal is "RST";
  attribute SIGIS of irq          : signal is "INTR_LEVEL_HIGH";
  attribute SIGIS of s_axi_aclk   : signal is "CLK";
  attribute SIGIS of s_axi_aresetn: signal is "RST";


end v_ycrcb2rgb;

architecture synth of v_ycrcb2rgb is

  constant C_IS_EVAL : boolean := FALSE;  --No license for this core

  constant C_GENR_NUM_REGS     : integer := 8;              -- # of general registers
  constant C_TIME_NUM_REGS     : integer := 2;              -- # of timing registers
  constant C_CORE_NUM_REGS     : integer := 9;              -- # of core registers
  constant ZEROS               : std_logic_vector(31 downto 0) := (others => '0');
  constant ONES                : std_logic_vector(31 downto 0) := (others => '1');

  constant C_LOAD_INIT_FILE    : integer := 0;

  ------------------------------------------------------------------------
  -- Register Write Mask. 
  -- 1=writable bit
  -- 0=read-only bit
  ------------------------------------------------------------------------
  constant C_GENR_AXI_WRITE        : slv_array(0 to C_GENR_NUM_REGS-1) :=
  (
    x"c000_003f", --00
    x"0001_000f", --04
    x"0000_000f", --08
    x"0001_000f", --0C
    x"0000_0000", --10
    x"0000_0000", --14
    x"0000_0000", --18
    x"0000_0000"  --1C
  );

  constant C_TIME_AXI_WRITE        : slv_array(0 to C_TIME_NUM_REGS-1) :=
  (
    x"ffff_ffff", --20
    x"0000_0007"  --24
  );

  constant C_CORE_AXI_WRITE        : slv_array(0 to C_CORE_NUM_REGS-1) := 
  (
    x"0000_ffff", --100
    x"0000_ffff", --104
    x"ffff_ffff", --108
    x"ffff_ffff", --10C
    x"ffff_ffff", --110
    x"0001_ffff", --114
    x"0001_ffff", --118
    x"0001_ffff", --11C
    x"0001_ffff"  --120
  );

  ------------------------------------------------------------------------
  -- Default register values/ Constant mode mapping
  ------------------------------------------------------------------------
  constant C_GENR_DEFAULT      : slv_array(0 to C_GENR_NUM_REGS-1) :=
  (
--  others => (others => '0')
    conv_std_logic_vector(1-C_HAS_AXI4_LITE, 32), --00
    x"0000_0000", --04
    x"0000_0000", --08
    x"0000_0000", --0C
    x"0000_0000", --10
    x"0000_0000", --14
    x"0000_0000", --18
    x"0000_0000"  --1C
  );
  constant C_TIME_DEFAULT      : slv_array(0 to C_TIME_NUM_REGS-1) :=
  (
--    others => (others => '0')
    conv_std_logic_vector(C_ACTIVE_ROWS, 16) & conv_std_logic_vector(C_ACTIVE_COLS, 16),  --20
    x"0000_0000" --24
  );
  constant C_CORE_DEFAULT      : slv_array(0 to C_CORE_NUM_REGS-1) := 
  (
--    others => (others => '0')
    conv_std_logic_vector(C_RGBMAX, 32),  --100
    conv_std_logic_vector(C_RGBMIN, 32),  --104
    conv_std_logic_vector(C_ROFFSET,32),  --108
    conv_std_logic_vector(C_GOFFSET,32),  --10c
    conv_std_logic_vector(C_BOFFSET,32),  --110
    conv_std_logic_vector(C_ACOEF,  32),  --114
    conv_std_logic_vector(C_BCOEF,  32),  --118
    conv_std_logic_vector(C_CCOEF,  32),  --11C
    conv_std_logic_vector(C_DCOEF,  32)   --120
  );

  ------------------------------------------------------------------------
  -- Double Buffer -each bit=1 means that the register will be double
  -- buffered and updated (when control[1] = '1' and reg_update = '1')
  ------------------------------------------------------------------------
  constant C_GENR_DBUFFER      : slv_array(0 to C_GENR_NUM_REGS-1) :=
  (
--    others => (others => '0')
    x"0000_000c", --00
    x"0000_0000", --04
    x"0000_0000", --08
    x"0000_0000", --0C
    x"0000_0000", --10
    x"0000_0000", --14
    x"0000_0000", --18
    x"0000_0000"  --1C
  );
  constant C_TIME_DBUFFER      : slv_array(0 to C_TIME_NUM_REGS-1) :=
  (
--    others => (others => '0')
    x"ffff_ffff", --20
    x"0000_0007"  --24
  );
  constant C_CORE_DBUFFER      : slv_array(0 to C_CORE_NUM_REGS-1) := 
  (
    x"0000_ffff", --100
    x"0000_ffff", --104
    x"ffff_ffff", --108
    x"ffff_ffff", --10c
    x"ffff_ffff", --110
    x"0001_ffff", --114
    x"0001_ffff", --118
    x"0001_ffff", --11C
    x"0001_ffff"  --120
  );

  signal genr_control_regs     : slv_array(0 to C_GENR_NUM_REGS-1) := (others => (others => '0'));
  signal genr_status_regs      : slv_array(0 to C_GENR_NUM_REGS-1) := (others => (others => '0'));

  signal time_control_regs     : slv_array(0 to C_TIME_NUM_REGS-1) := (others => (others => '0'));
  signal time_status_regs      : slv_array(0 to C_TIME_NUM_REGS-1) := (others => (others => '0'));

  signal core_control_regs     : slv_array(0 to C_CORE_NUM_REGS-1) := (others => (others => '0'));
  signal core_status_regs      : slv_array(0 to C_CORE_NUM_REGS-1) := (others => (others => '0'));
 
  signal reset                 : std_logic;
  signal resetn                : std_logic;
  signal core_d                : std_logic;

  signal reg_update            : std_logic := '0';

  signal ipif_addr_out         : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
  signal ipif_data_out         : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
  signal ipif_rnw_out          : std_logic;

  signal sclr                : std_logic := '0';
  signal frame_completed     : std_logic := '0';
  signal control             : std_logic_vector(31 downto 0) := conv_std_logic_vector(1, 32);  -- SW Enabled
  signal status              : std_logic_vector(16 downto 0) := (others => '0');
  signal error               : std_logic_vector( 3 downto 0) := (others => '0');
  signal sysdebug_0          : std_logic_vector(31 downto 0) := (others => '0');
  signal sysdebug_1          : std_logic_vector(31 downto 0) := (others => '0');
  signal sysdebug_2          : std_logic_vector(31 downto 0) := (others => '0');    
  signal active_rows         : std_logic_vector(12 downto 0) := conv_std_logic_vector(C_ACTIVE_ROWS, 13);
  signal active_cols         : std_logic_vector(12 downto 0) := conv_std_logic_vector(C_ACTIVE_COLS, 13);

  signal rgbmax_reg          : std_logic_vector(15 downto 0) := conv_std_logic_vector(C_RGBMAX,  16);   --100
  signal rgbmin_reg          : std_logic_vector(15 downto 0) := conv_std_logic_vector(C_RGBMIN,  16);   --104
  signal roffset_reg         : std_logic_vector(31 downto 0) := conv_std_logic_vector(C_ROFFSET, 32);   --108
  signal goffset_reg         : std_logic_vector(31 downto 0) := conv_std_logic_vector(C_GOFFSET, 32);   --10c
  signal boffset_reg         : std_logic_vector(31 downto 0) := conv_std_logic_vector(C_BOFFSET, 32);   --110
  signal acoef_reg           : std_logic_vector(16 downto 0) := conv_std_logic_vector(C_ACOEF,   17);   --114
  signal bcoef_reg           : std_logic_vector(16 downto 0) := conv_std_logic_vector(C_BCOEF,   17);   --118
  signal ccoef_reg           : std_logic_vector(16 downto 0) := conv_std_logic_vector(C_CCOEF,   17);   --11C
  signal dcoef_reg           : std_logic_vector(16 downto 0) := conv_std_logic_vector(C_DCOEF,   17);   --120

  
begin

  ------------------------------------------
  -- set padding bit value to 0
  ------------------------------------------

  DEFAULT: IF (C_M_AXIS_VIDEO_TDATA_WIDTH /= C_M_AXIS_VIDEO_DATA_WIDTH*3) GENERATE

  m_axis_video_tdata(C_M_AXIS_VIDEO_TDATA_WIDTH-1 downto C_M_AXIS_VIDEO_DATA_WIDTH*3 ) <= (OTHERS => '0');
  
  END GENERATE; --DEFAULT

  --m_axis_video_tdata <= (OTHERS => '0');


  ------------------------------------------
  -- Toggly intc_if output
  ------------------------------------------
  intc_if <= genr_status_regs(2)(3 downto 0) & genr_status_regs(1)(16) & genr_status_regs(1)(3 downto 0);

  ------------------------------------------
  -- instantiate video control
  ------------------------------------------
  U_VIDEO_CTRL: entity v_tc_v5_01_a.video_ctrl
    generic map(
      C_FAMILY            => C_FAMILY,
      C_HAS_AXI4_LITE     => C_HAS_AXI4_LITE,
      C_SRESET_LENGTH     => 1,
      C_S_AXI_ADDR_WIDTH  => C_S_AXI_ADDR_WIDTH,
      C_S_AXI_DATA_WIDTH  => C_S_AXI_DATA_WIDTH,

      -- may not need the C_IS_EVAL - can put the xlpp directly in.
      C_IS_EVAL           => C_IS_EVAL,
  
      C_GENR_NUM_REGS     => C_GENR_NUM_REGS,             -- # of general registers
      C_TIME_NUM_REGS     => C_TIME_NUM_REGS,             -- # of timing registers
      C_CORE_NUM_REGS     => C_CORE_NUM_REGS,             -- # of core registers
  
      C_GENR_AXI_WRITE    => C_GENR_AXI_WRITE,
      C_TIME_AXI_WRITE    => C_TIME_AXI_WRITE,
      C_CORE_AXI_WRITE    => C_CORE_AXI_WRITE,
  
      C_GENR_DEFAULT      => C_GENR_DEFAULT,
      C_TIME_DEFAULT      => C_TIME_DEFAULT,
      C_CORE_DEFAULT      => C_CORE_DEFAULT,
  
      C_GENR_DBUFFER      => C_GENR_DBUFFER,
      C_TIME_DBUFFER      => C_TIME_DBUFFER,
      C_CORE_DBUFFER      => C_CORE_DBUFFER,

      C_TIMEOUT_HOURS     => 8,           
      C_TIMEOUT_MINS      => 0,            
      C_VERSION_MAJOR     => 6,                           -- Major Version number
      C_VERSION_MINOR     => 1,                           -- Minor Version Number
      C_VERSION_REVISION  => 0,                           -- Version Revision character (EDK)
      C_COREGEN_PATCH     => 0,                           -- Coregen patch number
      C_REVISION_NUMBER   => 1                            -- Internal build number
    )
    port map (
       aclk          => s_axi_aclk,
       aclk_en       => s_axi_aclken, 
       aresetn       => s_axi_aresetn,

       vid_aclk      => aclk,   
       vid_aclk_en   => aclken, 
       vid_aresetn   => aresetn,

       reg_update    => reg_update,

       irq           => irq,
       resetn_out    => resetn, -- core soft reset not synched to frame
       core_d_out    => core_d, 

       -- Used to drive reading/writing RAMs/FFs in the IP core
       ipif_addr_out => ipif_addr_out,
       ipif_rnw_out  => ipif_rnw_out,
       ipif_data_out => ipif_data_out,

       genr_control_regs     => genr_control_regs,
       genr_status_regs      => genr_status_regs,

       time_control_regs     => time_control_regs,
       time_status_regs      => time_status_regs,

       core_control_regs     => core_control_regs,
       core_status_regs      => core_status_regs,

--   -- AXI Write Address Channel Signals
       s_axi_awaddr  => s_axi_awaddr,
       s_axi_awvalid => s_axi_awvalid,
       s_axi_awready => s_axi_awready,
--   -- AXI Write Channel Signals
       s_axi_wdata   => s_axi_wdata,
       s_axi_wstrb   => s_axi_wstrb,
       s_axi_wvalid  => s_axi_wvalid,
       s_axi_wready  => s_axi_wready,
--   -- AXI Write Response Channel Signals
       s_axi_bresp   => s_axi_bresp,
       s_axi_bvalid  => s_axi_bvalid,
       s_axi_bready  => s_axi_bready,
--   -- AXI Read Address Channel Signals
       s_axi_araddr  => s_axi_araddr,
       s_axi_arvalid => s_axi_arvalid,
       s_axi_arready => s_axi_arready,
--   -- AXI Read Data Channel Signals
       s_axi_rdata   => s_axi_rdata,
       s_axi_rresp   => s_axi_rresp,
       s_axi_rvalid  => s_axi_rvalid,
       s_axi_rready  => s_axi_rready
    );
  
  sclr <= not resetn;

  genr_status_regs(1)(status'high downto 0) <= status;   
  genr_status_regs(2)(error'high downto 0)  <= error;   
  genr_status_regs(5)                       <= sysdebug_0;   
  genr_status_regs(6)                       <= sysdebug_1;   
  genr_status_regs(7)                       <= sysdebug_2;   

  control           <= genr_control_regs(0);   

  active_rows       <= time_control_regs(0)(28 downto 16);
  active_cols       <= time_control_regs(0)(12 downto 0);

  rgbmax_reg      <= core_control_regs(0)(15 downto 0);
  rgbmin_reg      <= core_control_regs(1)(15 downto 0);
  roffset_reg     <= core_control_regs(2)(31 downto 0);
  goffset_reg     <= core_control_regs(3)(31 downto 0);
  boffset_reg     <= core_control_regs(4)(31 downto 0);
  acoef_reg       <= core_control_regs(5)(16 downto 0);
  bcoef_reg       <= core_control_regs(6)(16 downto 0);
  ccoef_reg       <= core_control_regs(7)(16 downto 0);
  dcoef_reg       <= core_control_regs(8)(16 downto 0);

  ycrcb2rgb_top_inst:  entity v_ycrcb2rgb_v6_01_a.ycrcb2rgb_top
    generic map (
      C_HAS_AXI4_LITE            => C_HAS_AXI4_LITE,
      C_HAS_DEBUG                => C_HAS_DEBUG,
      C_S_AXIS_VIDEO_DATA_WIDTH  => C_S_AXIS_VIDEO_DATA_WIDTH,
      C_S_AXIS_VIDEO_FORMAT	 => C_S_AXIS_VIDEO_FORMAT,
      C_S_AXIS_VIDEO_TDATA_WIDTH => C_S_AXIS_VIDEO_TDATA_WIDTH,
      C_M_AXIS_VIDEO_DATA_WIDTH  => C_M_AXIS_VIDEO_DATA_WIDTH,
      C_M_AXIS_VIDEO_FORMAT	 => C_M_AXIS_VIDEO_FORMAT,
      C_M_AXIS_VIDEO_TDATA_WIDTH => C_M_AXIS_VIDEO_TDATA_WIDTH,
      C_ACTIVE_COLS              => C_ACTIVE_COLS,
      C_ACTIVE_ROWS              => C_ACTIVE_ROWS,
      C_MWIDTH                   => C_MWIDTH,
      C_COEF_RANGE               => C_COEF_RANGE,
      C_ACOEF                    => C_ACOEF,
      C_BCOEF                    => C_BCOEF,
      C_CCOEF                    => C_CCOEF,
      C_DCOEF                    => C_DCOEF,
      C_ROFFSET                  => C_ROFFSET,
      C_GOFFSET                  => C_GOFFSET,
      C_BOFFSET                  => C_BOFFSET,
      C_HAS_CLIP                 => C_HAS_CLIP,
      C_HAS_CLAMP                => C_HAS_CLAMP,
      C_RGBMAX                   => C_RGBMAX,
      C_RGBMIN                   => C_RGBMIN,
      C_FAMILY                   => C_FAMILY
    )
    port map (
      clk               => aclk,
      ce                => aclken,
      sclr              => sclr,
      core_d            => core_d,
      s_axis_tdata      => s_axis_video_tdata,
      s_axis_tvalid     => s_axis_video_tvalid,
      s_axis_tlast      => s_axis_video_tlast,
      s_axis_tuser_sof  => s_axis_video_tuser_sof,
      s_axis_tready     => s_axis_video_tready,
      m_axis_tdata      => m_axis_video_tdata,
      m_axis_tvalid     => m_axis_video_tvalid,
      m_axis_tlast      => m_axis_video_tlast,
      m_axis_tuser_sof  => m_axis_video_tuser_sof,
      m_axis_tready     => m_axis_video_tready,
      register_update   => reg_update,
      control           => control,   
      status            => status,   
      error             => error,   
      sysdebug_0        => sysdebug_0,   
      sysdebug_1        => sysdebug_1,   
      sysdebug_2        => sysdebug_2,   
      active_rows       => active_rows,   
      active_cols       => active_cols,
      rgbmax            => rgbmax_reg,
      rgbmin            => rgbmin_reg,
      roffset           => roffset_reg,
      goffset           => goffset_reg,
      boffset           => boffset_reg,
      acoef             => acoef_reg,
      bcoef             => bcoef_reg,
      ccoef             => ccoef_reg,
      dcoef             => dcoef_reg
    );
  
end synth;