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-- 
-- Filename - debug.vhd 
-- Author -   Steven Elzinga, Xilinx 
-- Creation - March 2, 2012 
-- 
-- Description -  
-- This module implements the simple ramp test-pattern generator 
-- and the data, valid, eol, sof muxes. 
-- Inputs: vid_*_in signals are inputs from the input buffer 
--         core_*_in signals are inputs from the processing core 
--  
-- For test-pattern generation the "core" sof, eol, valid signals are 
-- used to ensure the module generates a test-pattern with the programmed  
-- active_size even when the input signals are corrupted or missing. 
 
 
library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
 
entity debug is 
  generic ( 
    DATA_WIDTH                 : integer := 8;   -- Component Width: (8, 10, 12, 16) 
    C_M_AXIS_VIDEO_TDATA_WIDTH : integer := 24;  -- (8, 16, 24, 32, 40, 48) 
    C_M_AXIS_VIDEO_FORMAT      : integer := 2);  -- 0 YUV 422, 1 YUV 444, 2 RGB, 3 YUV 420, 12 Bayer sensor supported 
  port( 
    clk            :  in std_logic; 
    ce             :  in std_logic; 
    sclr           :  in std_logic; 
                    
    test_pattern   :  in std_logic;  -- 1: core output replaced with ramp signal. bypass takes precedence over test_pattern. 
    bypass         :  in std_logic;  -- 1: input is forwarded to the output without any processing other than IWIDTH to OWDITH conversion. 
                    
    active_rows    :  in std_logic_vector(12 downto 0); 
    active_cols    :  in std_logic_vector(12 downto 0); 
    out_fifo_afull :  in std_logic := '0'; 
                    
                    
    vid_data_in    :  in std_logic_vector((C_M_AXIS_VIDEO_TDATA_WIDTH/DATA_WIDTH)*(DATA_WIDTH)-1 downto 0); 
    vid_valid_in   :  in std_logic; 
    vid_eol_in     :  in std_logic;  
    vid_sof_in     :  in std_logic;     
                    
    core_data_in   :  in std_logic_vector((C_M_AXIS_VIDEO_TDATA_WIDTH/DATA_WIDTH)*(DATA_WIDTH)-1 downto 0); 
    core_valid_in  :  in std_logic; 
    core_eol_in    :  in std_logic; 
    core_sof_in    :  in std_logic; 
    core_eof_in    :  in std_logic; 
                    
    sysdebug0      : out std_logic_vector(31 downto 0); 
    sysdebug1      : out std_logic_vector(31 downto 0); 
    sysdebug2      : out std_logic_vector(31 downto 0); 
                    
    vid_data_out   : out std_logic_vector((C_M_AXIS_VIDEO_TDATA_WIDTH/DATA_WIDTH)*(DATA_WIDTH)-1 downto 0) := (others => '0'); 
    vid_valid_out  : out std_logic; 
    vid_eol_out    : out std_logic;  
    vid_sof_out    : out std_logic);     
end debug; 
 
architecture rtl of debug is 
 
-- max function came from MemXlib_utils.  In order to not complicate 
-- the HDL file structure at this time, I included the function 
-- here instead of having to rely on library declaration, compile scripts, 
-- etc 
   function max(a, b:integer) return integer is 
   begin 
      if (a>b) then  
         return a; 
      else 
         return b; 
      end if; 
   end; 
 
  type mem_array is array (0 to 7) of std_logic_vector(23 downto 0); 
  type debug_states is (s0, s1, b2, t2); 
 
--  The vid_data_in, core_data_in and core_data_out are structured as: 
--  MSB ... LSB 
--   (R, B, G) 
 
  constant yuv_array : mem_array := 
  (X"80_80_08",  -- 4:4:4 VUY / Cr Cb Y, Black 
   X"22_36_91",  -- 4:4:4 VUY / Cr Cb Y, Green 
   X"6E_F0_29",  -- 4:4:4 VUY / Cr Cb Y, Blue 
   X"08_A6_AA",  -- 4:4:4 VUY / Cr Cb Y, Cyan 
   X"F0_5A_51",  -- 4:4:4 VUY / Cr Cb Y, Red 
   X"92_08_D2",  -- 4:4:4 VUY / Cr Cb Y, Yellow 
   X"DE_CA_6A",  -- 4:4:4 VUY / Cr Cb Y, Magenta 
   X"80_80_EB"); -- 4:4:4 VUY / Cr Cb Y, White 
 
  constant num_components   : integer := (C_M_AXIS_VIDEO_TDATA_WIDTH/DATA_WIDTH); 
  constant vid_data_width   : integer := num_components*DATA_WIDTH; 
 
  signal   color_pattern    : std_logic_vector(num_components*DATA_WIDTH - 1 downto 0) := (others => '0'); 
   
  signal   count_cols       : std_logic_vector(15 downto 0) := (others => '0'); 
  signal   count_rows       : std_logic_vector(15 downto 0) := (others => '0'); 
   
  signal   sysdebug0_i      : std_logic_vector(31 downto 0) := (others => '0'); 
  signal   sysdebug1_i      : std_logic_vector(31 downto 0) := (others => '0'); 
  signal   sysdebug2_i      : std_logic_vector(31 downto 0) := (others => '0'); 
   
  signal   CrCbSel          : std_logic := '0'; 
  signal   vid_valid_d      : std_logic := '0'; 
  signal   vid_valid        : std_logic := '0'; 
  signal   int_valid        : std_logic := '0'; 
  signal   int_eol          : std_logic := '0'; 
  signal   int_sof          : std_logic := '0'; 
  signal   int_eof          : std_logic := '0'; 
   
  signal   current_state    : debug_states; 
  signal   next_state       : debug_states; 
 
begin 
 
 
  CrCbSel   <= count_cols(0); 
  int_valid <= (bypass AND vid_valid_in) OR (NOT(bypass) AND (core_valid_in)); 
 
  sel_debug_output : process(clk) is 
  begin 
    if clk'event and clk = '1' then 
      if sclr = '1' then 
        current_state <= s0; 
        next_state <= s0; 
        count_cols <= (others => '0'); 
        count_rows <= (others => '0'); 
      elsif ce = '1' then 
        current_state <= next_state; 
        case current_state is 
          when s0 => 
--            fifo_re <= '1'; 
            vid_data_out <= core_data_in; 
            vid_valid    <= core_valid_in; 
            vid_eol_out  <= core_eol_in; 
            vid_sof_out  <= core_sof_in; 
            if bypass = '1' or test_pattern = '1' then 
              next_state <= s1; 
            end if; 
          when s1 => 
--            fifo_re <= '0'; 
            if int_valid = '0' then 
              if bypass = '1' then 
                next_state <= b2; 
              elsif test_pattern = '1' then 
                next_state <= t2; 
              else 
                next_state <= s0; 
              end if; 
            end if; 
          when b2 => 
            if bypass = '0' then 
              next_state <= s0; 
            end if; 
            if test_pattern = '1' then 
              next_state <= t2; 
            end if; 
   
            vid_data_out <= vid_data_in; 
            vid_valid    <= core_valid_in; 
            vid_eol_out  <= vid_eol_in; 
            vid_sof_out  <= vid_sof_in; 
 
          when t2 => 
            if test_pattern = '0' then 
              next_state <= s0; 
            end if; 
--------------------------------------------------------------- 
            if out_fifo_afull = '0' then 
              vid_valid_d   <= '1'; 
              vid_valid     <= vid_valid_d; 
              vid_data_out  <= color_pattern; 
              int_eol       <= '0'; 
              int_eof       <= '0'; 
              if count_rows = X"0000"  and count_cols = X"0000" then 
                int_sof <= '1'; 
              else 
                int_sof <= '0'; 
              end if; 
              vid_sof_out <= int_sof; 
              if count_cols = active_cols - 1 then 
                count_cols <= (others => '0'); 
                int_eol <= '1'; 
                vid_eol_out <= int_eol; 
                if count_rows = active_rows - 1 then 
                  count_rows <= (others => '0'); 
                  int_eof     <= '1'; 
                else 
                  count_rows  <= count_rows + '1'; 
                end if; 
              else 
                count_cols <= count_cols + '1'; 
                vid_eol_out <= int_eol; 
              end if; 
            else 
              vid_valid <= '0'; 
            end if; 
--------------------------------------------------------------- 
   
        end case; 
      end if; 
    end if; 
  end process; 
 
 
 
--  Use the count_cols(5), count_cols(6), count_cols(7) counter to assign RGB values 
--  The vid_data_in, core_data_in and core_data_out are structured as: 
--  MSB ... LSB 
--   (R, B, G) 
--  X"00_00_00" Black, 
--  X"00_00_FF" Green, 
--  X"00_FF_00" Blue, 
--  X"00_FF_FF" Cyan, 
--  X"FF_00_00" Red, 
--  X"FF_00_FF" Yellow, 
--  X"FF_FF_00" Magenta, 
--  X"FF_FF_FF" White 
   
  gen_color_pattern : if (C_M_AXIS_VIDEO_FORMAT = 2 or C_M_AXIS_VIDEO_FORMAT = 12) generate 
    create_rgb_test_ptrn : process (clk) is 
      variable ramp_test_pattern : std_logic_vector(max(12,DATA_WIDTH)-1 downto 0); 
    begin 
      if rising_edge(clk) then 
        if (sclr='1') then 
          color_pattern <= (others => '0'); 
        elsif (ce='1' and out_fifo_afull = '0') then -- and (int_valid = '1') then 
            if (count_rows < X"100") then 
                for i in 1 to num_components loop 
                  color_pattern(i*DATA_WIDTH-1 downto (i-1)*DATA_WIDTH) <= (others => count_cols(5+i)); 
                end loop; 
            else 
                ramp_test_pattern(max(12,DATA_WIDTH)-1 downto 0) := count_cols(DATA_WIDTH-1 downto 0) + (count_rows(11 downto 9) & (not(count_rows(8))) & count_rows(7 downto 0)); 
                for i in 1 to num_components loop 
                  color_pattern(i*DATA_WIDTH-1 downto (i-1)*DATA_WIDTH) <= ramp_test_pattern(DATA_WIDTH -1 downto 0);  
                end loop; 
            end if; -- check ramp counter 
        end if; -- ce / sclr 
      end if; -- clk 
    end process; 
  end generate; 
 
 
--  Use the count_cols counter as the address to get 
--  the color values from the constant array yuv_array   
 
  gen_yuv_test_pattern : if (C_M_AXIS_VIDEO_FORMAT /= 2 and C_M_AXIS_VIDEO_FORMAT /= 12) generate 
    create_yuv_test_ptrn : process (clk) is 
      variable ramp_test_pattern : std_logic_vector(max(12,DATA_WIDTH)-1 downto 0) := (others => '0'); 
    begin 
      if rising_edge(clk) then 
        if (sclr='1') then 
          color_pattern <= (others => '0'); 
        elsif (ce='1' and out_fifo_afull = '0') then 
          if (count_rows < X"100") then 
            if C_M_AXIS_VIDEO_FORMAT = 1 then 
              color_pattern(3*DATA_WIDTH-1 downto 3*DATA_WIDTH-8) <= 
                yuv_array(conv_integer(count_cols(8 downto 6)))(23 downto 16); 
              color_pattern(2*DATA_WIDTH-1 downto 2*DATA_WIDTH-8) <= 
                yuv_array(conv_integer(count_cols(8 downto 6)))(15 downto 8); 
              color_pattern(DATA_WIDTH-1 downto DATA_WIDTH-8) <= 
                yuv_array(conv_integer(count_cols(8 downto 6)))(7 downto 0); 
            else -- YUV 422 and 420 
              case CrCbSel is 
                when '0' => 
                  color_pattern(2*DATA_WIDTH-1 downto 2*DATA_WIDTH-8) <= 
                    yuv_array(conv_integer(count_cols(8 downto 6)))(23 downto 16); 
                  color_pattern(DATA_WIDTH-1 downto DATA_WIDTH-8) <= 
                    yuv_array(conv_integer(count_cols(8 downto 6)))(7 downto 0); 
                when '1' => 
                  color_pattern(2*DATA_WIDTH-1 downto 2*DATA_WIDTH-8) <= 
                    yuv_array(conv_integer(count_cols(8 downto 6)))(15 downto 8); 
                  color_pattern(DATA_WIDTH-1 downto DATA_WIDTH-8) <= 
                    yuv_array(conv_integer(count_cols(8 downto 6)))(7 downto 0); 
                when others => 
                  null; 
              end case; 
            end if; 
          else 
            ramp_test_pattern(max(12,DATA_WIDTH)-1 downto 0) := count_cols(DATA_WIDTH-1 downto 0) + (count_rows(11 downto 9) & (not(count_rows(8))) & count_rows(7 downto 0)); 
            color_pattern(DATA_WIDTH-1 downto 0) <= ramp_test_pattern(DATA_WIDTH -1 downto 0);  
            for i in 2 to num_components loop 
              color_pattern(i*8-1 downto (i-1)*8) <= X"80"; -- Any LSBs when data width is greater than 8 never get any value other than '0'  
            end loop; 
          end if; -- check ramp counter 
        end if; -- ce / sclr 
      end if; -- clk 
    end process; 
  end generate; 
   
  sysdebug_registers : process(clk) is 
  begin 
    if rising_edge(clk) then 
      if (sclr='1') then 
        sysdebug0_i <= (others => '0'); 
        sysdebug1_i <= (others => '0'); 
        sysdebug2_i <= (others => '0'); 
      elsif (ce='1') then 
        if bypass = '1' and test_pattern = '0' then 
          if (core_valid_in = '1') then 
            if (vid_sof_in = '1') then 
              sysdebug0_i <= sysdebug0_i + '1';  -- count frames 
            end if; -- eof 
            if (vid_eol_in = '1') then 
              sysdebug1_i <= sysdebug1_i + '1';  -- count lines 
            end if; -- eol 
            sysdebug2_i <= sysdebug2_i + '1';    -- count pixels 
          end if; -- core_valid_in 
        elsif test_pattern = '1' then 
          if (vid_valid = '1') then 
            if (int_eof = '1') then 
              sysdebug0_i <= sysdebug0_i + '1';  -- count frames 
            end if; -- eof 
            if (int_eol = '1') then 
              sysdebug1_i <= sysdebug1_i + '1';  -- count lines 
            end if; -- eol 
            sysdebug2_i <= sysdebug2_i + '1';    -- count pixels 
          end if; 
        else 
          if (core_valid_in = '1') then 
            if (core_eof_in = '1') then 
              sysdebug0_i <= sysdebug0_i + '1';  -- count frames 
            end if; -- eof 
            if (core_eol_in = '1') then 
              sysdebug1_i <= sysdebug1_i + '1';  -- count lines 
            end if; -- eol 
            sysdebug2_i <= sysdebug2_i + '1';    -- count pixels 
          end if; -- core_valid_in 
        end if; 
      end if;   -- ce and valid in 
    end if;     -- clk 
  end process;  -- sysdebug_registers 
   
  vid_valid_out <= vid_valid; 
  sysdebug0     <= sysdebug0_i; 
  sysdebug1     <= sysdebug1_i; 
  sysdebug2     <= sysdebug2_i; 
   
end rtl;