www.pudn.com > taxi_counter.rar > hex7.vhd

library ieee; 
use ieee.std_logic_1164.all; 
 
entity hex7 is 
	port(   clk : in  std_logic; 
			hex : out std_logic_vector(3 downto 0)); 
end hex7; 
 
architecture art of hex7 is 
	signal cnt:integer range 0 to 9; 
begin 
  process(clk) 
  begin 
	if rising_edge(clk)then 
		if cnt=9 then 
			cnt<=0; 
		else cnt<=cnt+1; 
		end if; 
	else null; 
	end if; 
	case cnt is 
		when 0 =>hex<= "0000"; 
		when 1 =>hex<= "0001"; 
  		when 2 =>hex<= "0010"; 
  		when 3 =>hex<= "0011"; 
		when 4 =>hex<= "0100"; 
   		when 5 =>hex<= "0101"; 
   		when 6 =>hex<= "0110"; 
   		when 7 =>hex<= "0111"; 
   		when 8 =>hex<= "1000"; 
   		when 9 =>hex<= "1001"; 
		when others =>hex<= "0000"; 
	end case; 
  end process; 
end art;