www.pudn.com > shiboqi.rar > mv.cmp, change:2013-03-27,size:968b


--Copyright (C) 1991-2010 Altera Corporation 
--Your use of Altera Corporation's design tools, logic functions  
--and other software and tools, and its AMPP partner logic  
--functions, and any output files from any of the foregoing  
--(including device programming or simulation files), and any  
--associated documentation or information are expressly subject  
--to the terms and conditions of the Altera Program License  
--Subscription Agreement, Altera MegaCore Function License  
--Agreement, or other applicable license agreement, including,  
--without limitation, that your use is for the sole purpose of  
--programming logic devices manufactured by Altera and sold by  
--Altera or its authorized distributors.  Please refer to the  
--applicable agreement for further details. 
 
 
component mv 
	PORT 
	( 
		address		: IN STD_LOGIC_VECTOR (3 DOWNTO 0); 
		clock		: IN STD_LOGIC  := '1'; 
		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0) 
	); 
end component;