www.pudn.com > shiboqi.rar > fuzhi.v, change:2013-03-24,size:1549b


module fuzhi (clk,rst_n,data_out,fuzhi1,fuzhi2,fuzhi3,fuzhi4); 
input clk,rst_n; 
input[9:0] data_out; 
output[3:0] fuzhi1; 
output[3:0]fuzhi2; 
output[3:0]fuzhi3; 
output[3:0]fuzhi4; 
 
reg[25:0] cnt; 
always@(posedge clk or negedge rst_n) 
begin 
	if(!rst_n) cnt<=1'b0; 
	else if(cnt==26'd49_999_999) 
		cnt<=1'b0; 
	else  
		cnt<=cnt+1'b1; 
end 
		 
wire t=(cnt==26'd49_999_999) ? 1'b1:1'b0;	 
	 
reg[9:0] datamax,datamin; 
reg[10:0]fuzhi_r; 
reg[9:0] data_r; 
 
always@(posedge clk or negedge rst_n) 
begin 
	if(!rst_n) 
		data_r<=1'b0; 
	else if(t) 
		begin 
			datamax<=1'b1; 
			datamin<=10'd1023; 
			fuzhi_r<=((datamax-datamin)*2-10'd130); 
		end 
	else 
		begin 
			data_r<=data_out; 
			if(datamax<data_r)	 
				datamax<=data_r; 
			else if(datamin>data_r)  
				datamin<=data_r; 
		end 
end 
 
reg[10:0] fuzhi; 
reg[3:0] fuzhi1_r,fuzhi2_r,fuzhi3_r,fuzhi4_r; 
reg[15:0] temp; 
integer i; 
 
always@(posedge clk) 
begin 
	fuzhi=fuzhi_r; 
	temp = 0; 
	for(i = 0;i < 10;i = i + 1) 
	begin 
		 temp = {temp[14:0],fuzhi[10]};  
		 if(temp[3:0] > 4'd4)  
			temp[3:0] = temp[3:0]+4'd3; 
         if(temp[7:4] > 4'd4)  
            temp[7:4] = temp[7:4]+4'd3; 
         if(temp[11:8] > 4'd4)  
            temp[11:8] = temp[11:8]+4'd3; 
         if(temp[15:12] > 4'd4)  
            temp[15:12] = temp[15:12]+4'd3; 
		 fuzhi=fuzhi<<1;   
          {fuzhi1_r,fuzhi2_r,fuzhi3_r,fuzhi4_r}={temp[14:0],fuzhi[0]}; 
      end 
end 
 
assign fuzhi1=fuzhi1_r; 
assign fuzhi2=fuzhi2_r; 
assign fuzhi3=fuzhi3_r; 
assign fuzhi4=fuzhi4_r; 
 
endmodule