www.pudn.com > shiboqi.rar > advga.v, change:2013-03-27,size:4155b


module advga (clk,rst_n,hsync_vga,vsync_vga,clk_out,r,g,b,data_in,sw,s_w); 
input clk,rst_n; 
input[9:0] data_in; 
input[7:0] sw; 
input[3:0] s_w; 
output hsync_vga; 
output vsync_vga; 
output clk_out; 
output [2:0] r,g,b; 
 
wire wen; 
wire cfd; 
wire[7:0] sw_an; 
wire[10:0] x_pos,y_pos; 
wire[9:0] data_out,ram_data; 
wire[12:0] ram_addr; 
wire valid; 
wire [31:0]rom1data; 
wire[6:0]rom1addr; 
wire[3:0] fuzhi1,fuzhi2,fuzhi3,fuzhi4; 
wire[3:0] pinlv1,pinlv2,pinlv3,pinlv4; 
 
wire [31:0]rom2data; 
wire [7:0]rom2addr; 
wire [31:0]rom3data; 
wire [7:0]rom3addr; 
wire [31:0]rom4data; 
wire [7:0]rom4addr; 
wire [31:0]rom5data; 
wire [7:0]rom5addr; 
wire [31:0]rom6data; 
wire [5:0]rom6addr; 
wire [63:0]rom7data; 
wire [8:0]rom7addr; 
wire [31:0]rom8data; 
wire [7:0]rom8addr; 
wire [31:0]rom9data; 
wire  [7:0]rom9addr; 
wire [31:0]rom10data; 
wire [7:0]rom10addr; 
wire [31:0]rom11data; 
wire [7:0]rom11addr; 
wire[143:0]rom12data; 
wire [5:0]rom12addr; 
wire [151:0]rom13data; 
wire[5:0]rom13addr; 
wire[31:0]rom14data; 
wire [3:0]rom14addr; 
wire[47:0]rom15data; 
wire [3:0]rom15addr; 
AD m1   (.clk(clk), 
		 .rst_n(rst_n), 
		 .data_in(data_in), 
		 .data_out(data_out), 
		 .clk_out(clk_out) 
		 ); 
		  
vga m2  (.clk(clk), 
		 .rst_n(rst_n), 
		 .valid(valid), 
		 .hsync_vga(hsync_vga), 
		 .vsync_vga(vsync_vga), 
		 .x_pos(x_pos), 
		 .y_pos(y_pos), 
		 ); 
 
ram_control m3( 
		.clk(clk), 
		.rst_n(rst_n), 
		.ram_data(ram_data), 
		.x_pos(x_pos), 
		.y_pos(y_pos), 
        .ram_addr(ram_addr), 
		.wen(wen), 
		.data_out(data_out), 
        .r(r), 
        .g(g), 
        .b(b), 
         .s_w(s_w), 
        .cfd(cfd), 
        .sw_an(sw_an), 
        .valid(valid), 
		.rom1data(rom1data), 
		.rom1addr(rom1addr), 
		.rom2data(rom2data), 
		.rom2addr(rom2addr), 
		.rom3data(rom3data), 
		.rom3addr(rom3addr), 
		.rom4data(rom4data), 
		.rom4addr(rom4addr), 
		.rom5data(rom5data), 
		.rom5addr(rom5addr), 
		.rom6data(rom6data), 
		.rom6addr(rom6addr), 
		.rom7data(rom7data), 
		.rom7addr(rom7addr), 
		.rom8data(rom8data), 
		.rom8addr(rom8addr), 
		.rom9data(rom9data), 
		.rom9addr(rom9addr), 
		.rom10data(rom10data), 
		.rom10addr(rom10addr), 
		.rom11data(rom11data), 
		.rom11addr(rom11addr), 
		.rom12data(rom12data), 
		.rom12addr(rom12addr), 
		.rom13data(rom13data), 
		.rom13addr(rom13addr), 
		.rom14data(rom14data), 
		.rom14addr(rom14addr), 
		.rom15data(rom15data), 
		.rom15addr(rom15addr), 
		.fuzhi1(fuzhi1), 
		.fuzhi2(fuzhi2), 
		.fuzhi3(fuzhi3), 
		.fuzhi4(fuzhi4), 
		.pinlv1(pinlv1), 
		.pinlv2(pinlv2), 
		.pinlv3(pinlv3), 
		.pinlv4(pinlv4) 
		); 
		 
ram_1 m4  ( 
			.address(ram_addr), 
			.clock(clk), 
			.data(data_out), 
			.wren(wen), 
			.q(ram_data) 
			); 
			 
fuzhi1 m5 ( 
		.address(rom1addr), 
		.clock(clk), 
		.q(rom1data) 
		  ); 
fuzhi m6( 
		.clk(clk), 
		.rst_n(rst_n), 
		.data_out(data_out), 
		.fuzhi1(fuzhi1), 
		.fuzhi2(fuzhi2), 
		.fuzhi3(fuzhi3), 
		.fuzhi4(fuzhi4) 
		); 
shuzi2 m7( 
		.address_a(rom2addr), 
		.address_b(rom3addr), 
		.clock(clk), 
		.q_a(rom2data), 
		.q_b(rom3data)	 
		); 
shuzi2 m8( 
		.address_a(rom4addr), 
		.address_b(rom5addr), 
		.clock(clk),           
		.q_a(rom4data), 
		.q_b(rom5data)	 
		); 
pinlv m9 ( 
		.address(rom6addr), 
		.clock(clk), 
		.q(rom6data) 
		  ); 
sbq m10 ( 
		.address(rom7addr), 
		.clock(clk), 
		.q(rom7data) 
		  ); 
pinlv_n m11( 
			.clk(clk), 
			.rst_n(rst_n), 
			.cfd(cfd), 
			.pinlv1(pinlv1), 
			.pinlv2(pinlv2), 
			.pinlv3(pinlv3), 
			.pinlv4(pinlv4) 
			); 
shuzi2 m12( 
		.address_a(rom8addr), 
		.address_b(rom9addr), 
		.clock(clk), 
		.q_a(rom8data), 
		.q_b(rom9data)	 
		); 
shuzi2 m13( 
		.address_a(rom10addr), 
		.address_b(rom11addr), 
		.clock(clk),           
		.q_a(rom10data), 
		.q_b(rom11data)	 
		); 
anjian m14( 
		.clk(clk), 
		.rst_n(rst_n), 
		.sw(sw), 
		.sw_an(sw_an) 
		); 
	 
mvdiv m15( 
		.address(rom12addr), 
		.clock(clk), 
		.q(rom12data) 
		);
usdiv m16( 
		.address(rom13addr), 
		.clock(clk), 
		.q(rom13data) 
		); 
mv m17( 
		.address(rom14addr), 
		.clock(clk), 
		.q(rom14data) 
		); 
khz m18( 
		.address(rom15addr), 
		.clock(clk), 
		.q(rom15data) 
		);		 
endmodule