www.pudn.com > shiboqi.rar > advga.qsf, change:2013-07-04,size:14641b


# -------------------------------------------------------------------------- # 
# 
# Copyright (C) 1991-2010 Altera Corporation 
# Your use of Altera Corporation's design tools, logic functions  
# and other software and tools, and its AMPP partner logic  
# functions, and any output files from any of the foregoing  
# (including device programming or simulation files), and any  
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License  
# Subscription Agreement, Altera MegaCore Function License  
# Agreement, or other applicable license agreement, including,  
# without limitation, that your use is for the sole purpose of  
# programming logic devices manufactured by Altera and sold by  
# Altera or its authorized distributors.  Please refer to the  
# applicable agreement for further details. 
# 
# -------------------------------------------------------------------------- # 
# 
# Quartus II 
# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Full Version 
# Date created = 16:24:08  March 18, 2013 
# 
# -------------------------------------------------------------------------- # 
# 
# Notes: 
# 
# 1) The default values for assignments are stored in the file: 
#		advga_assignment_defaults.qdf 
#    If this file doesn't exist, see file: 
#		assignment_defaults.qdf 
# 
# 2) Altera recommends that you do not modify this file. This 
#    file is updated automatically by the Quartus II software 
#    and any changes you make may be lost or overwritten. 
# 
# -------------------------------------------------------------------------- # 
 
 
set_global_assignment -name FAMILY "Cyclone II" 
set_global_assignment -name DEVICE EP2C35F484C8 
set_global_assignment -name TOP_LEVEL_ENTITY advga 
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2" 
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:24:08  MARCH 18, 2013" 
set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2" 
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga 
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" 
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" 
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" 
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" 
set_location_assignment PIN_AB19 -to data_in[9] 
set_location_assignment PIN_R22 -to data_in[8] 
set_location_assignment PIN_V20 -to data_in[7] 
set_location_assignment PIN_T22 -to data_in[6] 
set_location_assignment PIN_U20 -to data_in[5] 
set_location_assignment PIN_U21 -to data_in[4] 
set_location_assignment PIN_AB20 -to data_in[3] 
set_location_assignment PIN_P18 -to data_in[2] 
set_location_assignment PIN_V21 -to data_in[1] 
set_location_assignment PIN_U22 -to data_in[0] 
set_location_assignment PIN_Y19 -to b[2] 
set_location_assignment PIN_AA18 -to b[1] 
set_location_assignment PIN_W15 -to b[0] 
set_location_assignment PIN_Y14 -to g[2] 
set_location_assignment PIN_Y16 -to g[1] 
set_location_assignment PIN_W14 -to g[0] 
set_location_assignment PIN_AB13 -to hsync_vga 
set_location_assignment PIN_AB14 -to r[2] 
set_location_assignment PIN_U13 -to r[1] 
set_location_assignment PIN_AA13 -to r[0] 
set_location_assignment PIN_L2 -to rst_n 
set_location_assignment PIN_Y17 -to vsync_vga 
set_location_assignment PIN_L1 -to clk 
set_location_assignment PIN_E19 -to clk_out 
set_global_assignment -name MISC_FILE "C:/Users/Administrator/Desktop/advga/advga.dpf" 
set_global_assignment -name ENABLE_SIGNALTAP ON 
set_global_assignment -name USE_SIGNALTAP_FILE stp2.stp 
set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to clk -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=4096" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=4096" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0 
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" 
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 
set_global_assignment -name MISC_FILE "E:/advga/advga.dpf" 
set_global_assignment -name MISC_FILE "C:/Users/Administrator/Desktop/ad1/advga.dpf" 
set_location_assignment PIN_AB15 -to sw[0] 
set_location_assignment PIN_AB11 -to sw[1] 
set_location_assignment PIN_D8 -to sw[2] 
set_location_assignment PIN_E9 -to sw[3] 
set_location_assignment PIN_M22 -to sw[4] 
set_location_assignment PIN_A12 -to sw[5] 
set_global_assignment -name MIF_FILE usdiv.mif 
set_global_assignment -name MIF_FILE mvdiv.mif 
set_global_assignment -name VERILOG_FILE advga.v 
set_global_assignment -name VERILOG_FILE vga.v 
set_global_assignment -name VERILOG_FILE ram_control.v 
set_global_assignment -name VERILOG_FILE AD.v 
set_global_assignment -name QIP_FILE ram_1.qip 
set_global_assignment -name SIGNALTAP_FILE stp1.stp 
set_global_assignment -name VERILOG_FILE fuzhi.v 
set_global_assignment -name MIF_FILE fuzhi1.mif 
set_global_assignment -name QIP_FILE fuzhi1.qip 
set_global_assignment -name MIF_FILE shuzi.mif 
set_global_assignment -name QIP_FILE shuzi.qip 
set_global_assignment -name QIP_FILE shuzi2.qip 
set_global_assignment -name MIF_FILE pinlv.mif 
set_global_assignment -name QIP_FILE pinlv.qip 
set_global_assignment -name MIF_FILE sbq.mif 
set_global_assignment -name QIP_FILE sbq.qip 
set_global_assignment -name VERILOG_FILE pinlv_n.v 
set_global_assignment -name VERILOG_FILE anjian.v 
set_global_assignment -name QIP_FILE mvdiv.qip 
set_global_assignment -name QIP_FILE usdiv.qip 
set_global_assignment -name MIF_FILE mv.mif 
set_global_assignment -name QIP_FILE mv.qip 
set_global_assignment -name MIF_FILE khz.mif 
set_global_assignment -name QIP_FILE khz.qip 
set_global_assignment -name MISC_FILE "E:/FPGA/gongcheng/作业本/数字示波器/advga.dpf" 
set_global_assignment -name SIGNALTAP_FILE stp2.stp 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "ram_control:m3|shuyi[0]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "ram_control:m3|shuyi[1]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "ram_control:m3|shuyi[2]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "ram_control:m3|shuyi[3]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "ram_control:m3|shuyi[4]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "ram_control:m3|shuyi[5]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "ram_control:m3|shuyi[6]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "ram_control:m3|shuyi[7]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "ram_control:m3|shuyi[8]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "ram_control:m3|shuyi[9]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "ram_control:m3|y_pos[0]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "ram_control:m3|y_pos[10]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "ram_control:m3|y_pos[1]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "ram_control:m3|y_pos[2]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "ram_control:m3|y_pos[3]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "ram_control:m3|y_pos[4]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "ram_control:m3|y_pos[5]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "ram_control:m3|y_pos[6]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "ram_control:m3|y_pos[7]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "ram_control:m3|y_pos[8]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "ram_control:m3|y_pos[9]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "ram_control:m3|shuyi[0]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "ram_control:m3|shuyi[1]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "ram_control:m3|shuyi[2]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "ram_control:m3|shuyi[3]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "ram_control:m3|shuyi[4]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "ram_control:m3|shuyi[5]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "ram_control:m3|shuyi[6]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "ram_control:m3|shuyi[7]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "ram_control:m3|shuyi[8]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "ram_control:m3|shuyi[9]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "ram_control:m3|y_pos[0]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "ram_control:m3|y_pos[10]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "ram_control:m3|y_pos[1]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "ram_control:m3|y_pos[2]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "ram_control:m3|y_pos[3]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "ram_control:m3|y_pos[4]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "ram_control:m3|y_pos[5]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "ram_control:m3|y_pos[6]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "ram_control:m3|y_pos[7]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "ram_control:m3|y_pos[8]" -section_id auto_signaltap_0 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "ram_control:m3|y_pos[9]" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=21" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=21" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=89" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=15620" -section_id auto_signaltap_0 
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=14993" -section_id auto_signaltap_0 
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top